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[209.132.180.67]) by mx.google.com with ESMTP id i128si18875656pfc.0.2019.03.27.04.16.40; Wed, 27 Mar 2019 04:16:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="ZwYqS/o7"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733054AbfC0LPi (ORCPT + 99 others); Wed, 27 Mar 2019 07:15:38 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33170 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729489AbfC0LPi (ORCPT ); Wed, 27 Mar 2019 07:15:38 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2RBEY2j071681; Wed, 27 Mar 2019 06:14:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553685274; bh=vCV/hMZ+QzIZpg8WE23m5Dr0O1VTmo9wuJreqOkka38=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=ZwYqS/o7TZyigJ40OUP6Bih5PeYm8j2ubmwjYhhWm+BYJCjML79shRMMG4DkNfhch 61IR+x44XQ3S3Nr8lOTDSBGTY8NFOnuxnnLwCp1fzOEDQ24HOxSa1qzAejVmEg0gF7 0qrqqM8Sg+GYcaKLpaPxT5HqwrC7WE/rPj2yuRJQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2RBEYBI115017 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 27 Mar 2019 06:14:34 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 27 Mar 2019 06:14:34 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 27 Mar 2019 06:14:34 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x2RBEUXb032891; Wed, 27 Mar 2019 06:14:31 -0500 Subject: Re: [PATCH v2 1/4] ARM: davinci: fix cpufreq registration on da850-evm To: Bartosz Golaszewski , Adam Ford CC: Bartosz Golaszewski , Kevin Hilman , Rob Herring , Mark Rutland , David Lechner , devicetree , Linux Kernel Mailing List , arm-soc References: <20190322133105.5945-1-brgl@bgdev.pl> <20190322133105.5945-2-brgl@bgdev.pl> From: Sekhar Nori Message-ID: Date: Wed, 27 Mar 2019 16:44:29 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bart, On 26/03/19 11:21 PM, Bartosz Golaszewski wrote: > wt., 26 mar 2019 o 15:00 Adam Ford napisaƂ(a): >> >> On Fri, Mar 22, 2019 at 8:31 AM Bartosz Golaszewski wrote: >>> >>> From: Bartosz Golaszewski >>> >>> The system_rev variable is never set on davinci and is always 0, so >>> we're using the default max operating point of 300MHz. The cvdd supply >>> comes from the tps6507 pmic and the voltage can go all the way to 1.3V >>> so the maximum supported rate should be 456MHz. >> >> My understanding is that only certain revisions of the silicon can go >> to 456MHz. The L138's Datasheet lists both a 456 and 375 version. I >> cannot find a way to read a register to determine which version of the >> silicon is available. Maybe Sekhar can confirm. >> > > Commit 28bd2c341120 ("davinci: am18x/da850/omap-l138 evm: add support > for higher speed grades") mentions the following: > > --- > U-Boot on the EVM sets up ATAG_REVISION to inform the OS > regarding the speed grade supported by the silicon. We use > this information to pass on the speed grade information to > the SoC code. > --- > > Should the system_rev somehow reflect that revision? Any way I can check it? Can you check if the procedure in doc/README.davinci in U-Boot sources still works? Environment Variables ===================== The DA850 EVM allows the user to specify the maximum cpu clock allowed by the silicon, in Hz, via an environment variable "maxcpuclk". The maximum clock rate allowed depends on the silicon populated on the EVM. Please make sure you understand the restrictions placed on this clock in the device specific datasheet before setting up this variable. This information is passed to the Linux kernel using the ATAG_REVISION atag. If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK is used to obtain this information. Thanks, Sekhar