Received: by 2002:ac0:bc90:0:0:0:0:0 with SMTP id a16csp5451490img; Wed, 27 Mar 2019 08:45:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkv/8yWqeieWST41Nsnh7w0uORNQoXMKZyGeCZ8YEJyIPa3uLICv8y90Mo3QN66OsmWYyl X-Received: by 2002:a63:4241:: with SMTP id p62mr17817776pga.379.1553701553707; Wed, 27 Mar 2019 08:45:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553701553; cv=none; d=google.com; s=arc-20160816; b=sGBiIQzE1thReMLe4t4qiwjR2IDaO5QH3jgnn/46Bzth/1SlJpEUscdDbd66AkKYhN 4uaQ2ncoP+32J6lO+HhrUhaY1azlEmiQXUPksjNuaJ9a755vvIU0L2Tbpd5siQR5kLSZ 0L8zvchYLol6ZOAJCHhZTw9zvvHayV14k6rEJj8F+b3FeXFmjSepppETua3wyy4i7Tl+ IZsIquzdXToRro+Z4w8duBnM6lwpcO7tmyWeXuWITlLXyNa6vDkAzqYMcnTvncCSW1uX bgYp89kIp83/LF1yuP3KZtKS4SHI45wkqPk8Tp6mE0faWv9GTqZTRukw+FTL2xWdWdmF 0TrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:date:cc:to:from:subject:message-id; bh=/VnfmY4V7uKbGrgQamUr97O9zU+toGwGssdFh2sP95U=; b=oRqJfjHlPxi51j+XbTWsJ5sZPbGSVzEZxzxUBEA01hZzB7BrtFDm0DMvBKMxyE9f69 +Fngblpi2B53P6JNBZ7ZbotnpI6rB9gIsMiN97yKdYn5PEu4i71LrkllLZZYckvIyU34 LNKhzV21WX7aFaum5HDhkeSp0hjnq4PNfMj0B5yBn9XMklj1JN1E1C/uSmH1E5JhAJ0G bJXGgn5JFHfAqC0PIS57ttkw7w8jfuwwiLLU4jCTQ091hfVCkUnD21e/D2K7vYikgApe /Qy/u/xm3bJ93RxkPo/urMTf4ug3uWmtdcHcrjOSxRbX+CBf1wOYRsvvZAf2Aergz3ws qXvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l187si18587622pfc.43.2019.03.27.08.45.37; Wed, 27 Mar 2019 08:45:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727551AbfC0Pou (ORCPT + 99 others); Wed, 27 Mar 2019 11:44:50 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:52129 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727397AbfC0Pou (ORCPT ); Wed, 27 Mar 2019 11:44:50 -0400 Received: from kresse.hi.pengutronix.de ([2001:67c:670:100:1d::2a]) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1h9AjI-00068E-8i; Wed, 27 Mar 2019 16:44:40 +0100 Message-ID: <1553701479.2561.38.camel@pengutronix.de> Subject: Re: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup From: Lucas Stach To: Abel Vesa , Sudeep Holla , Marc Zyngier , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , "catalin.marinas@arm.com" , Will Deacon , "Rafael J. Wysocki" , Lorenzo Pieralisi , Fabio Estevam , Aisheng Dong Cc: dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , Linux Kernel Mailing List , "linux-pm@vger.kernel.org" Date: Wed, 27 Mar 2019 16:44:39 +0100 In-Reply-To: <1553692845-20983-1-git-send-email-abel.vesa@nxp.com> References: <1553692845-20983-1-git-send-email-abel.vesa@nxp.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::2a X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Abel, Am Mittwoch, den 27.03.2019, 13:21 +0000 schrieb Abel Vesa: > This work is a workaround I'm looking into (more as a background task) > in order to add support for cpuidle on i.MX8MQ based platforms. > > The main idea here is getting around the missing GIC wake_request signal > (due to integration design issue) by waking up a each individual core through > some dedicated SW power-up bits inside the power controller (GPC) right before > every IPI is requested for that each individual core. Just a general comment, without going into the details of this series: this issue is not only affecting IPIs, but also MSIs terminated at the GIC. Currently MSIs are terminated at the PCIe core, but terminating them at the GIC is clearly preferable, as this allows assigning CPU affinity to individual MSIs and lowers IRQ service overhead. I'm not sure what the consequences are for upstream Linux support yet, but we should keep in mind that having a workaround for IPIs is only solving part of the issue. Regards, Lucas