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[209.132.180.67]) by mx.google.com with ESMTP id q88si19580531pfa.222.2019.03.27.20.19.15; Wed, 27 Mar 2019 20:19:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728248AbfC1DSf (ORCPT + 99 others); Wed, 27 Mar 2019 23:18:35 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:32849 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726176AbfC1DSe (ORCPT ); Wed, 27 Mar 2019 23:18:34 -0400 X-UUID: 6a516fcfc32e4ec0b12309d87313533a-20190328 X-UUID: 6a516fcfc32e4ec0b12309d87313533a-20190328 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1770464845; Thu, 28 Mar 2019 11:18:28 +0800 Received: from MTKMBS01DR.mediatek.inc (172.21.101.111) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 28 Mar 2019 11:18:26 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01dr.mediatek.inc (172.21.101.111) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 28 Mar 2019 11:18:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 28 Mar 2019 11:18:26 +0800 Message-ID: <1553743106.14682.6.camel@mtksdaap41> Subject: Re: [PATCH v2 01/25] arm64: dts: add display nodes for mt8183 From: CK Hu To: CC: , , , , , , , , , , , Date: Thu, 28 Mar 2019 11:18:26 +0800 In-Reply-To: <1553667561-25447-2-git-send-email-yongqiang.niu@mediatek.com> References: <1553667561-25447-1-git-send-email-yongqiang.niu@mediatek.com> <1553667561-25447-2-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Wed, 2019-03-27 at 14:18 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add display nodes for mt8183 I think this patch should be after binding document patch. You should define the compatible string then you could add device node. > > Change-Id: I9ce7081a2159ec7cc199999285b0390b01de43fe Remove 'Change-Id' when you upstream. Regards, CK > Signed-off-by: Yongqiang Niu > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 107 +++++++++++++++++++++++++++++++ > 1 file changed, 107 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 75c4881..f219dbd 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -16,6 +16,14 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + ovl0 = &ovl0; > + ovl_2l0 = &ovl0_2l; > + ovl_2l1 = &ovl1_2l; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -317,6 +325,105 @@ > #clock-cells = <1>; > }; > > + display_components: dispsys@14000000 { > + compatible = "mediatek,mt8183-display"; > + reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + }; > + > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + mediatek,larb = <&larb0>; > + }; > + > + ovl0_2l: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; > + mediatek,larb = <&larb0>; > + }; > + > + ovl1_2l: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; > + mediatek,larb = <&larb0>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu M4U_PORT_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma1"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb0>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > smi_common: smi@14019000 { > compatible = "mediatek,mt8183-smi-common", "syscon"; > reg = <0 0x14019000 0 0x1000>;