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Thu, 28 Mar 2019 04:16:04 -0700 Received: from [172.23.37.108] (helo=xhdnagasure40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1h9T0u-0000TW-5v; Thu, 28 Mar 2019 04:16:04 -0700 From: Naga Sureshkumar Relli To: , , CC: , , , , , , , Naga Sureshkumar Relli Subject: [LINUX PATCH 1/3] dt-bindings: spi: Add device tree binding documentation for Zynq QSPI controller Date: Thu, 28 Mar 2019 16:46:00 +0530 Message-ID: <1553771760-2011-1-git-send-email-naga.sureshkumar.relli@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(376002)(396003)(136003)(39860400002)(2980300002)(199004)(189003)(2201001)(8676002)(6666004)(356004)(36756003)(478600001)(7696005)(51416003)(2906002)(5660300002)(336012)(426003)(77096007)(47776003)(305945005)(4326008)(106466001)(106002)(186003)(54906003)(110136005)(16586007)(63266004)(8936002)(107886003)(9786002)(36386004)(486006)(2616005)(316002)(476003)(126002)(50226002)(50466002)(48376002)(81156014)(81166006)(26005)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR02MB5248;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;A:1;MX:1; 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Reviewed-by: Rob Herring Signed-off-by: Naga Sureshkumar Relli --- .../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt new file mode 100644 index 0000000..16b734a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt @@ -0,0 +1,25 @@ +Xilinx Zynq QSPI controller Device Tree Bindings +------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynq-qspi-1.0". +- reg : Physical base address and size of QSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi: spi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + reg = <0xe000d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + num-cs = <1>; + }; -- 2.7.4