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[209.132.180.67]) by mx.google.com with ESMTP id c4si1396640pgk.353.2019.03.29.01.53.58; Fri, 29 Mar 2019 01:54:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729224AbfC2IxN (ORCPT + 99 others); Fri, 29 Mar 2019 04:53:13 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:56712 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729109AbfC2IxM (ORCPT ); Fri, 29 Mar 2019 04:53:12 -0400 Received: from localhost (unknown [IPv6:2a01:e0a:2c:6930:5cf4:84a1:2763:fe0d]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: bbrezillon) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 25C6C27D87F; Fri, 29 Mar 2019 08:53:11 +0000 (GMT) Date: Fri, 29 Mar 2019 09:53:07 +0100 From: Boris Brezillon To: Vignesh Raghavendra Cc: Naga Sureshkumar Relli , "broonie@kernel.org" , "bbrezillon@kernel.org" , "linux-spi@vger.kernel.org" , "dwmw2@infradead.org" , "marek.vasut@gmail.com" , "richard@nod.at" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "michal.simek@xilinx.com" , "nagasuresh12@gmail.com" Subject: Re: [LINUX PATCH 2/3] spi: spi-mem: call spi_mem_default_supports_op() first Message-ID: <20190329095307.02d970fd@collabora.com> In-Reply-To: References: <1553771784-3364-1-git-send-email-naga.sureshkumar.relli@xilinx.com> <20190328205522.272e1da6@collabora.com> Organization: Collabora X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 29 Mar 2019 13:50:26 +0530 Vignesh Raghavendra wrote: > Hi Boris, > > On 29/03/19 1:25 AM, Boris Brezillon wrote: > > On Thu, 28 Mar 2019 16:46:24 +0530 > > Naga Sureshkumar Relli wrote: > > > >> Call spi_mem_default_supports_op() first, before calling controller > >> specific ctlr->supports_op(). > >> With this, controller drivers can drop checking the buswidths again. > > > > No, this was done on purpose, in case the controller does not want the > > default check to be applied (say it does not need bus-width props to > > be defined and has another way to check if a device can be accessed in > > dual, quad or octal mode). > > Sorry, I don't understand here. > Based on capabilities declared in spi_device->mode, m25p80 driver will > claim appropriate SNOR_HWCAPS_*. SPI NOR layer chooses opcodes based > on that for which m25p80 layer populates buswidths. Well, that test in m25p80 should go away and be replaced by a proper spi_mem_supports_op() iteration on all modes reported as supported by the *chip* (I think that's what I did in my series merging m25p80 code into the spi-nor core). But that's not really related to the problem we're discussing here. > > So, I don't really expect any mismatch in spi_mem_default_supports_op() > in the case you mentioned. Or did I miss something? Maybe something SPI > NAND specific? Nothing NAND specific, just something controller specific and how we want to deal with buswidth detection. Most memory devices expose their caps in some way (be it ID-based detection or using some kind of caps/parameters table), so they know what they're capable of. SPI controllers know what they're capable of, of course. The only part that remains unknown for buswidth negotiation is how things are wired on the board. I keep thinking that defining buswidth in the DT (using spi-{tx,rx}-bus-width) should only be done if there are board-related limiting factors (some IO pins not routed). If you look at the code, SPI_{TX,RX}_{DUAL,QUAD,OCTAL} flags are only set if the spi-{tx,rx}-bus-width props are defined. The idea behind making spi_mem_default_supports_op() optional is to let new drivers implement a new scheme where missing spi-{tx,rx}-bus-width does not necessarily mean "use regular SPI mode".