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[209.132.180.67]) by mx.google.com with ESMTP id p3si1817836plr.45.2019.03.29.05.43.25; Fri, 29 Mar 2019 05:43:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729598AbfC2Mmg (ORCPT + 99 others); Fri, 29 Mar 2019 08:42:36 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57364 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729537AbfC2Mmd (ORCPT ); Fri, 29 Mar 2019 08:42:33 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2TCfkoi028202; Fri, 29 Mar 2019 13:42:24 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2rf4ycg3f6-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 29 Mar 2019 13:42:24 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AED5D31; Fri, 29 Mar 2019 12:42:23 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 89C312A5E; Fri, 29 Mar 2019 12:42:23 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 29 Mar 2019 13:42:23 +0100 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.435.0; Fri, 29 Mar 2019 13:42:23 +0100 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland , , , , , Benjamin Gaignard , Yannick Fertre , Philippe Cornu Subject: [PATCH v1 1/2] ARM: dts: stm32: add cec pins muxing on stm32mp157 Date: Fri, 29 Mar 2019 13:41:54 +0100 Message-ID: <1553863315-6652-2-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553863315-6652-1-git-send-email-yannick.fertre@st.com> References: <1553863315-6652-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-29_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new pin muxing for cec. Signed-off-by: Yannick Fertré --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 9104896..54fe2ad 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -157,6 +157,15 @@ }; }; + cec_pins_b: cec-1 { + pins { + pinmux = ; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ -- 2.7.4