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[209.132.180.67]) by mx.google.com with ESMTP id u20si1813119pga.71.2019.03.29.05.44.58; Fri, 29 Mar 2019 05:45:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729614AbfC2MoQ (ORCPT + 99 others); Fri, 29 Mar 2019 08:44:16 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57501 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729464AbfC2MoO (ORCPT ); Fri, 29 Mar 2019 08:44:14 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2TCfkuH028203; Fri, 29 Mar 2019 13:44:05 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2rf4ycg3p8-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 29 Mar 2019 13:44:05 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 96ED131; Fri, 29 Mar 2019 12:44:04 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 723002A63; Fri, 29 Mar 2019 12:44:04 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 29 Mar 2019 13:44:04 +0100 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.435.0; Fri, 29 Mar 2019 13:44:04 +0100 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Maxime Coquelin , Alexandre Torgue , Rob Herring , Mark Rutland , , , , , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , Fabrice Gasnier Subject: [PATCH v1 2/2] ARM: dts: stm32: enable display on stm32mp157c-dk1 board Date: Fri, 29 Mar 2019 13:43:58 +0100 Message-ID: <1553863438-6720-3-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553863438-6720-1-git-send-email-yannick.fertre@st.com> References: <1553863438-6720-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-29_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable hdmi bridge sii9022 & display controller. Signed-off-by: Yannick Fertré --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 696a533..f483600 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -37,6 +37,14 @@ }; }; + v1v2_hdmi: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + v3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "v3v3"; @@ -44,6 +52,14 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + v3v3_hdmi: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; ðernet0 { @@ -74,6 +90,32 @@ status = "okay"; /delete-property/dmas; /delete-property/dma-names; + + hdmi-transmitter@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-1 = <<dc_pins_sleep_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + }; }; &i2c4 { @@ -96,6 +138,20 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in>; + }; + }; +}; + &rng1 { status = "okay"; }; -- 2.7.4