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From:   Benjamin Gaignard <benjamin.gaignard@linaro.org>
Date:   Fri, 29 Mar 2019 15:03:05 +0100
Message-ID: <CA+M3ks52k=Gj=i662DPzc0OV593xUnRfMiLVH+Bjc63CSSE20Q@mail.gmail.com>
Subject: Re: [PATCH] media: platform: stm32: wait end of transmission
To:     =?UTF-8?Q?Yannick_Fertr=C3=A9?= <yannick.fertre@st.com>
Cc:     Mauro Carvalho Chehab <mchehab@kernel.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Alexandre Torgue <alexandre.torgue@st.com>,
        linux-media@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Benjamin Gaignard <benjamin.gaignard@st.com>,
        Philippe Cornu <philippe.cornu@st.com>
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Le ven. 29 mars 2019 =C3=A0 13:40, Yannick Fertr=C3=A9 <yannick.fertre@st.c=
om> a =C3=A9crit :
>
> It is mandatory to write CEC_CFGR only when CECEN=3D0. To protect
> transmission, a check have been added to delayed logical address
> modification. This patch is necessary tp pass all tests of compliance.

Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>

>
> Signed-off-by: Yannick Fertr=C3=A9 <yannick.fertre@st.com>
> ---
>  drivers/media/platform/stm32/stm32-cec.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/media/platform/stm32/stm32-cec.c b/drivers/media/pla=
tform/stm32/stm32-cec.c
> index 7c496bc..8a86b2c 100644
> --- a/drivers/media/platform/stm32/stm32-cec.c
> +++ b/drivers/media/platform/stm32/stm32-cec.c
> @@ -56,6 +56,13 @@
>  #define ALL_TX_IT      (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
>  #define ALL_RX_IT      (RXEND | RXBR | RXACKE | RXOVR)
>
> +/*
> + * 400 ms is the time it takes for one 16 byte message to be
> + * transferred and 5 is the maximum number of retries. Add
> + * another 100 ms as a margin.
> + */
> +#define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
> +
>  struct stm32_cec {
>         struct cec_adapter      *adap;
>         struct device           *dev;
> @@ -188,7 +195,11 @@ static int stm32_cec_adap_log_addr(struct cec_adapte=
r *adap, u8 logical_addr)
>  {
>         struct stm32_cec *cec =3D adap->priv;
>         u32 oar =3D (1 << logical_addr) << 16;
> +       u32 val;
>
> +       /* Poll every 100=C2=B5s the register CEC_CR to wait end of trans=
mission */
> +       regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM)=
,
> +                                100, CEC_XFER_TIMEOUT_MS * 1000);
>         regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
>
>         if (logical_addr =3D=3D CEC_LOG_ADDR_INVALID)
> --
> 2.7.4
>
>
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