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Subject: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes
Thread-Topic: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes
Thread-Index: AQHU5xsXTkClBElNYkSLBv/JPYYQCg==
Date:   Sat, 30 Mar 2019 17:07:44 +0000
Message-ID: <20190330170725.24360-1-daniel.baluta@nxp.com>
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lpuart nodes are part of the ADMA subsystem. See Audio DMA
memory map in iMX8 QXP RM [1]

This patch is based on the dtsi file initially submitted by
Teo Hall in i.MX NXP internal tree.

[1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf

Signed-off-by: Teo Hall <teo.hall@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d=
ts/freescale/imx8qxp.dtsi
index 0cb939861a60..1adfe15c2ea5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -193,6 +193,39 @@
 			status =3D "disabled";
 		};
=20
+		adma_lpuart1: serial@5a070000 {
+			compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+			reg =3D <0x5a070000 0x1000>;
+			interrupts =3D <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent =3D <&gic>;
+			clocks =3D <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+			clock-names =3D "ipg";
+			power-domains =3D <&pd IMX_SC_R_UART_1>;
+			status =3D "disabled";
+		};
+
+		adma_lpuart2: serial@5a080000 {
+			compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+			reg =3D <0x5a080000 0x1000>;
+			interrupts =3D <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent =3D <&gic>;
+			clocks =3D <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+			clock-names =3D "ipg";
+			power-domains =3D <&pd IMX_SC_R_UART_2>;
+			status =3D "disabled";
+		}
+
+		adma_lpuart3: serial@5a090000 {
+			compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+			reg =3D <0x5a090000 0x1000>;
+			interrupts =3D <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent =3D <&gic>;
+			clocks =3D <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+			clock-names =3D "ipg";
+			power-domains =3D <&pd IMX_SC_R_UART_3>;
+			status =3D "disabled";
+		}
+
 		adma_i2c0: i2c@5a800000 {
 			compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 			reg =3D <0x5a800000 0x4000>;
--=20
2.17.1