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Date:   Mon, 1 Apr 2019 14:49:40 +0700
From:   Mark Brown <broonie@kernel.org>
To:     Sowjanya Komatineni <skomatineni@nvidia.com>
Cc:     thierry.reding@gmail.com, jonathanh@nvidia.com, talho@nvidia.com,
        robh+dt@kernel.org, mark.rutland@arm.com, kyarlagadda@nvidia.com,
        ldewangan@nvidia.com, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
        devicetree@vger.kernel.org
Subject: Re: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is
 reset to its default
Message-ID: <20190401074940.GL2059@sirena.org.uk>
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On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote:
> With SW CS, during transfer completion CS is de-asserted by writing the
> default command1 register value to SPI_COMMAND1 register. With this both
> mode and CS state are set at the same time and if current transfer mode
> is different to default SPI mode and if mode change happens prior to CS
> de-assert, clock polarity can change while CS is active before transfer
> finishes.

This is a bug fix so I'd expect it to be much earlier in the series
before any of the new features.

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