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Subject: Re: [PATCH v4] dt-bindings: gpu: add bindings for the ARM Mali
 Bifrost GPU
To:     Steven Price <steven.price@arm.com>, daniel@ffwll.ch,
        robh@kernel.org
Cc:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org
References: <20190401080949.14550-1-narmstrong@baylibre.com>
 <1640dd7b-3576-d9ce-0641-6b6a64a87275@arm.com>
From:   Neil Armstrong <narmstrong@baylibre.com>
Openpgp: preference=signencrypt
Autocrypt: addr=narmstrong@baylibre.com; prefer-encrypt=mutual; keydata=
 mQENBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP
 GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4
 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9
 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik
 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB
 AAG0KE5laWwgQXJtc3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT6JATsEEwEKACUC
 GyMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheABQJXDO2CAhkBAAoJEBaat7Gkz/iubGIH/iyk
 RqvgB62oKOFlgOTYCMkYpm2aAOZZLf6VKHKc7DoVwuUkjHfIRXdslbrxi4pk5VKU6ZP9AKsN
 NtMZntB8WrBTtkAZfZbTF7850uwd3eU5cN/7N1Q6g0JQihE7w4GlIkEpQ8vwSg5W7hkx3yQ6
 2YzrUZh/b7QThXbNZ7xOeSEms014QXazx8+txR7jrGF3dYxBsCkotO/8DNtZ1R+aUvRfpKg5
 ZgABTC0LmAQnuUUf2PHcKFAHZo5KrdO+tyfL+LgTUXIXkK+tenkLsAJ0cagz1EZ5gntuheLD
 YJuzS4zN+1Asmb9kVKxhjSQOcIh6g2tw7vaYJgL/OzJtZi6JlIW5AQ0ETVkGzwEIALyKDN/O
 GURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYpQTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXM
 coJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hi
 SvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY4yG6xI99NIPEVE9lNBXBKIlewIyVlkOa
 YvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoMMtsyw18YoX9BqMFInxqYQQ3j/HpVgTSv
 mo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUXoUk33HEAEQEAAYkBHwQYAQIACQUCTVkG
 zwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfnM7IbRuiSZS1unlySUVYu3SD6YBYnNi3G
 5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa33eDIHu/zr1HMKErm+2SD6PO9umRef8V8
 2o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCSKmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+
 RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJ
 C3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTTQbM0WUIBIcGmq38+OgUsMYu4NzLu7uZF
 Acmp6h8guQINBFYnf6QBEADQ+wBYa+X2n/xIQz/RUoGHf84Jm+yTqRT43t7sO48/cBW9vAn9
 GNwnJ3HRJWKATW0ZXrCr40ES/JqM1fUTfiFDB3VMdWpEfwOAT1zXS+0rX8yljgsWR1UvqyEP
 3xN0M/40Zk+rdmZKaZS8VQaXbveaiWMEmY7sBV3QvgOzB7UF2It1HwoCon5Y+PvyE3CguhBd
 9iq5iEampkMIkbA3FFCpQFI5Ai3BywkLzbA3ZtnMXR8Qt9gFZtyXvFQrB+/6hDzEPnBGZOOx
 zkd/iIX59SxBuS38LMlhPPycbFNmtauOC0DNpXCv9ACgC9tFw3exER/xQgSpDVc4vrL2Cacr
 wmQp1k9E0W+9pk/l8S1jcHx03hgCxPtQLOIyEu9iIJb27TjcXNjiInd7Uea195NldIrndD+x
 58/yU3X70qVY+eWbqzpdlwF1KRm6uV0ZOQhEhbi0FfKKgsYFgBIBchGqSOBsCbL35f9hK/JC
 6LnGDtSHeJs+jd9/qJj4WqF3x8i0sncQ/gszSajdhnWrxraG3b7/9ldMLpKo/OoihfLaCxtv
 xYmtw8TGhlMaiOxjDrohmY1z7f3rf6njskoIXUO0nabun1nPAiV1dpjleg60s3OmVQeEpr3a
 K7gR1ljkemJzM9NUoRROPaT7nMlNYQL+IwuthJd6XQqwzp1jRTGG26J97wARAQABiQM+BBgB
 AgAJBQJWJ3+kAhsCAikJEBaat7Gkz/iuwV0gBBkBAgAGBQJWJ3+kAAoJEHfc29rIyEnRk6MQ
 AJDo0nxsadLpYB26FALZsWlN74rnFXth5dQVQ7SkipmyFWZhFL8fQ9OiIoxWhM6rSg9+C1w+
 n45eByMg2b8H3mmQmyWztdI95OxSREKwbaXVapCcZnv52JRjlc3DoiiHqTZML5x1Z7lQ1T3F
 8o9sKrbFO1WQw1+Nc91+MU0MGN0jtfZ0Tvn/ouEZrSXCE4K3oDGtj3AdC764yZVq6CPigCgs
 6Ex80k6QlzCdVP3RKsnPO2xQXXPgyJPJlpD8bHHHW7OLfoR9DaBNympfcbQJeekQrTvyoASw
 EOTPKE6CVWrcQIztUp0WFTdRGgMK0cZB3Xfe6sOp24PQTHAKGtjTHNP/THomkH24Fum9K3iM
 /4Wh4V2eqGEgpdeSp5K+LdaNyNgaqzMOtt4HYk86LYLSHfFXywdlbGrY9+TqiJ+ZVW4trmui
 NIJCOku8SYansq34QzYM0x3UFRwff+45zNBEVzctSnremg1mVgrzOfXU8rt+4N1b2MxorPF8
 619aCwVP7U16qNSBaqiAJr4e5SNEnoAq18+1Gp8QsFG0ARY8xp+qaKBByWES7lRi3QbqAKZf
 yOHS6gmYo9gBmuAhc65/VtHMJtxwjpUeN4Bcs9HUpDMDVHdfeRa73wM+wY5potfQ5zkSp0Jp
 bxnv/cRBH6+c43stTffprd//4Hgz+nJcCgZKtCYIAPkUxABC85ID2CidzbraErVACmRoizhT
 KR2OiqSLW2x4xdmSiFNcIWkWJB6Qdri0Fzs2dHe8etD1HYaht1ZhZ810s7QOL7JwypO8dscN
 KTEkyoTGn6cWj0CX+PeP4xp8AR8ot4d0BhtUY34UPzjE1/xyrQFAdnLd0PP4wXxdIUuRs0+n
 WLY9Aou/vC1LAdlaGsoTVzJ2gX4fkKQIWhX0WVk41BSFeDKQ3RQ2pnuzwedLO94Bf6X0G48O
 VsbXrP9BZ6snXyHfebPnno/te5XRqZTL9aJOytB/1iUna+1MAwBxGFPvqeEUUyT+gx1l3Acl
 ZaTUOEkgIor5losDrePdPgE=
Organization: Baylibre
Message-ID: <d26f1ce9-c56c-5e51-37f5-0689aa198dc0@baylibre.com>
Date:   Mon, 1 Apr 2019 13:24:40 +0200
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Sender: linux-kernel-owner@vger.kernel.org
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On 01/04/2019 12:00, Steven Price wrote:
> On 01/04/2019 09:09, Neil Armstrong wrote:
>> Add the bindings for the Bifrost family of ARM Mali GPUs.
>>
>> The Bifrost GPU architecture is similar to the Midgard family,
>> but with a different Shader Core & Execution Engine structures.
>>
>> Bindings are based on the Midgard family bindings, but the inner
>> architectural changes makes it a separate family needing separate
>> bindings.
>>
>> The Bifrost GPUs are present in a number of recent SoCs, like the
>> Amlogic G12A Family, and many other vendors.
>> The Amlogic vendor specific compatible is added to handle the
>> specific IP integration differences and dependencies.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>>  .../bindings/gpu/arm,mali-bifrost.txt         | 92 +++++++++++++++++++
>>  1 file changed, 92 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
>>
>> Changes since v3:
>> - Added note about discoverable model/revision
>> - Enforced fixed defined irq order
>> - Fixed typo in accommodate
>>
>> Changes since v2:
>> - moved to a single compatible since HW is fully discoverable
>>
>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
>> new file mode 100644
>> index 000000000000..711c9ead17a2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
>> @@ -0,0 +1,92 @@
>> +ARM Mali Bifrost GPU
>> +====================
>> +
>> +Required properties:
>> +
>> +- compatible :
>> +  * Since Mali Bifrost GPU model/revision if fully discoverable by reading
>                                              ^^
> s/if/is/

Thanks for pointing this.

> 
>> +    some determined registers, must contain the following:
>> +    + "arm,mali-bifrost"
>> +  * which must be preceded by one of the following vendor specifics:
>> +    + "amlogic,meson-g12a-mali"
>> +
>> +- reg : Physical base address of the device and length of the register area.
>> +
>> +- interrupts : Contains the three IRQ lines required by Mali Bifrost devices,
>> +  in the following defined order.
>> +
>> +- interrupt-names : Contains the names of IRQ resources in this exact defined
>> +  order: "job", "mmu", "gpu".
> 
> Is there any point in having "interrupt-names" if we're fixing the
> order? Although I guess it helps match the Midgard bindings.

Exact.

Neil

> 
> Steve
> 
>> +
>> +Optional properties:
>> +
>> +- clocks : Phandle to clock for the Mali Bifrost device.
>> +
>> +- mali-supply : Phandle to regulator for the Mali device. Refer to
>> +  Documentation/devicetree/bindings/regulator/regulator.txt for details.
>> +
>> +- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
>> +  for details.
>> +
>> +- resets : Phandle of the GPU reset line.
>> +
>> +Vendor-specific bindings
>> +------------------------
>> +
>> +The Mali GPU is integrated very differently from one SoC to
>> +another. In order to accommodate those differences, you have the option
>> +to specify one more vendor-specific compatible, among:
>> +
>> +- "amlogic,meson-g12a-mali"
>> +  Required properties:
>> +  - resets : Should contain phandles of :
>> +    + GPU reset line
>> +    + GPU APB glue reset line
>> +
>> +Example for a Mali-G31:
>> +
>> +gpu@ffa30000 {
>> +	compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
>> +	reg = <0xffe40000 0x10000>;
>> +	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
>> +		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
>> +		     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
>> +	interrupt-names = "job", "mmu", "gpu";
>> +	clocks = <&clk CLKID_MALI>;
>> +	mali-supply = <&vdd_gpu>;
>> +	operating-points-v2 = <&gpu_opp_table>;
>> +	resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
>> +};
>> +
>> +gpu_opp_table: opp_table0 {
>> +	compatible = "operating-points-v2";
>> +
>> +	opp@533000000 {
>> +		opp-hz = /bits/ 64 <533000000>;
>> +		opp-microvolt = <1250000>;
>> +	};
>> +	opp@450000000 {
>> +		opp-hz = /bits/ 64 <450000000>;
>> +		opp-microvolt = <1150000>;
>> +	};
>> +	opp@400000000 {
>> +		opp-hz = /bits/ 64 <400000000>;
>> +		opp-microvolt = <1125000>;
>> +	};
>> +	opp@350000000 {
>> +		opp-hz = /bits/ 64 <350000000>;
>> +		opp-microvolt = <1075000>;
>> +	};
>> +	opp@266000000 {
>> +		opp-hz = /bits/ 64 <266000000>;
>> +		opp-microvolt = <1025000>;
>> +	};
>> +	opp@160000000 {
>> +		opp-hz = /bits/ 64 <160000000>;
>> +		opp-microvolt = <925000>;
>> +	};
>> +	opp@100000000 {
>> +		opp-hz = /bits/ 64 <100000000>;
>> +		opp-microvolt = <912500>;
>> +	};
>> +};
>>
>