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Mon, 1 Apr 2019 18:40:36 +0000 From: Sowjanya Komatineni To: Mark Brown CC: "thierry.reding@gmail.com" , Jonathan Hunter , Timo Alho , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "Krishna Yarlagadda" , Laxman Dewangan , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH V1 18/26] spi: tegra114: add support for hw based cs Thread-Topic: [PATCH V1 18/26] spi: tegra114: add support for hw based cs Thread-Index: AQHU5GIKKpTkIfSTtEWeqLFxMgMCeKYm9fSAgAC1kqA= Date: Mon, 1 Apr 2019 18:40:36 +0000 Message-ID: References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> <1553666207-11414-18-git-send-email-skomatineni@nvidia.com> <20190401074857.GK2059@sirena.org.uk> In-Reply-To: <20190401074857.GK2059@sirena.org.uk> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=skomatineni@nvidia.com; x-originating-ip: [216.228.112.22] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6d3ea233-67ee-437e-cb6a-08d6b6d18842 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(2017052603328)(7193020);SRVR:BYAPR12MB2710; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554144040; bh=TffHUIiyqlo13jA/W9t1Vw9GzK6ChcvvJJxr5fjySn0=; h=X-PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-microsoft-antispam:x-ms-traffictypediagnostic: x-microsoft-antispam-prvs:x-forefront-prvs: x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=c8oliPbXxpGuuBh7oomw4wdhrl+Y0bdku+3UmFmvw6bGcEcPwcQhTJxMO70DZcfH2 rjK+l+nAs0iknE/4ME3MzIaMQleDiRUNokluICTt0QNAYHbP3yTnujik5SoGZdwmb2 wnE57veMum/X3B8U8VQJ3AY48griyt+VTyicNthB859frXJbM/sF/rn3nSfA00DESN vd3OQMVYAjsYvf1dgkZIvtFJLjKxI5SXWibHl05KKVutXSFeFO0fjyYhwGY7Zlzx7f TWx5MBvoVDLy2TbutqCELwkC2EpbFDl+b8tiWV5kRbyk86fVr5QLmM4sMsSn3P9Nod Uk8SKmlEgSXRA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Tue, Mar 26, 2019 at 10:56:39PM -0700, Sowjanya Komatineni wrote: >=20 > > Tegra SPI driver default uses SW CS control for transfers and HW CS=20 > > control can be enabled through SPI client device node DT property=20 > > nvidia,enable-hw-based-cs and is used only for single transfers. > > Why have a property - if this feature works and is useful why would a sys= tem ever not want to use it? > > + single_xfer =3D list_is_singular(&msg->transfers); > > list_for_each_entry(xfer, &msg->transfers, transfer_list) { > > u32 cmd1; > > =20 > > reinit_completion(&tspi->xfer_completion); > > =20 > > - cmd1 =3D tegra_spi_setup_transfer_one(spi, xfer, is_first_msg); > > + cmd1 =3D tegra_spi_setup_transfer_one(spi, xfer, is_first_msg, > > + single_xfer); > > It's not sufficient to check if there's only one transfer, you also need = to make sure that the driver isn't using cs_change to use non-standard chip= select handling. Yes we can avoid DT and force to use HW CS incase of all single transfers w= ithout cs_change. Will update in next version.