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Date:   Tue, 02 Apr 2019 06:00:43 +0100
Message-ID: <86ef6l57d0.wl-marc.zyngier@arm.com>
From:   Marc Zyngier <marc.zyngier@arm.com>
To:     Heyi Guo <guoheyi@huawei.com>
Cc:     <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        wanghaibin 00208455 <wanghaibin.wang@huawei.com>
Subject: Re: MSI number limit for PCI hotplug under PCI bridge on ARM platform
In-Reply-To: <327ba551-2cbd-08bb-d4c1-107c3ff7d45d@huawei.com>
References: <327ba551-2cbd-08bb-d4c1-107c3ff7d45d@huawei.com>
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On Mon, 01 Apr 2019 14:55:52 +0100,
Heyi Guo <guoheyi@huawei.com> wrote:
> 
> Hi folks,
> 
> In current kernel implementation for ARM platform, all devices under
> one PCI bridge share a same device ID and the total number of MSI
> interrupts is fixed at the first time any child device is allocating
> MSI. However, this may cause failure of allocating MSI if the system
> supports device hot-plug under the PCI bridge, which is possible for
> ARM virtual machine with generic pcie-to-pci-bridge and kernel
> config HOTPLUG_PCI_SHPC enabled.
> 
> Does it make sense to add support for the above scenario? If it
> does, any suggestion for how to do that?

I don't think it makes much sense. You have the flexibility not to add
such a broken setup to your guests, and instead have enough pcie ports
so that you can always have an exact allocation and no DevID aliasing.

The alternative is to dynamically grow the ITT for a given DevID,
which cannot be done without unmapping it first. This in turn will
result in interrupts being lost while the DevID was unmapped, and
they'd need to be pessimistically reinjected. This also involves a
substantial amount of data structure repainting, as you're pretty much
guaranteed not to be able to reuse the same LPI range.

Given that this is arbitrarily self-inflicted, I'm not overly keen on
even trying to support this.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.