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[209.132.180.67]) by mx.google.com with ESMTP id i33si10263572pgb.99.2019.04.01.22.55.22; Mon, 01 Apr 2019 22:55:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727160AbfDBEyU (ORCPT + 99 others); Tue, 2 Apr 2019 00:54:20 -0400 Received: from mga14.intel.com ([192.55.52.115]:57641 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725778AbfDBEyT (ORCPT ); Tue, 2 Apr 2019 00:54:19 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 21:54:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,298,1549958400"; d="scan'208";a="157900878" Received: from hao-dev.bj.intel.com (HELO localhost) ([10.238.157.65]) by fmsmga004.fm.intel.com with ESMTP; 01 Apr 2019 21:54:17 -0700 Date: Tue, 2 Apr 2019 12:38:45 +0800 From: Wu Hao To: Moritz Fischer Cc: atull@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-api@vger.kernel.org Subject: Re: [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address. Message-ID: <20190402043845.GA24012@hao-dev> References: <1553483264-5379-1-git-send-email-hao.wu@intel.com> <1553483264-5379-2-git-send-email-hao.wu@intel.com> <20190401195447.GA1910@archbook> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190401195447.GA1910@archbook> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 01, 2019 at 12:54:47PM -0700, Moritz Fischer wrote: > Hi Wu, > > On Mon, Mar 25, 2019 at 11:07:28AM +0800, Wu Hao wrote: > > FME_PR_INTFC_ID is used as compat_id for fpga manager and region, > > but high 64 bits and low 64 bits of the compat_id are swapped by > > mistake. This patch fixes this problem by fixing register address. > > > > Signed-off-by: Wu Hao > > --- > > drivers/fpga/dfl-fme-mgr.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c > > index 76f3770..b3f7eee 100644 > > --- a/drivers/fpga/dfl-fme-mgr.c > > +++ b/drivers/fpga/dfl-fme-mgr.c > > @@ -30,8 +30,8 @@ > > #define FME_PR_STS 0x10 > > #define FME_PR_DATA 0x18 > > #define FME_PR_ERR 0x20 > > -#define FME_PR_INTFC_ID_H 0xA8 > > -#define FME_PR_INTFC_ID_L 0xB0 > > +#define FME_PR_INTFC_ID_L 0xA8 > > +#define FME_PR_INTFC_ID_H 0xB0 > > Does this handle endianess correct? Hi Moritz, This is just a bug fixing for wrong offsets given to these 2 registers according to spec. I think this is not endianess related, and per my understanding we don't need more code on endianess handling as that should be done inside the readq function already. :) Thanks Hao