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[209.132.180.67]) by mx.google.com with ESMTP id z9si11221720plo.118.2019.04.02.09.11.21; Tue, 02 Apr 2019 09:11:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731756AbfDBQIq (ORCPT + 99 others); Tue, 2 Apr 2019 12:08:46 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:53726 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731671AbfDBQIW (ORCPT ); Tue, 2 Apr 2019 12:08:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81684374; Tue, 2 Apr 2019 09:08:21 -0700 (PDT) Received: from e107981-ln.cambridge.arm.com (e107981-ln.cambridge.arm.com [10.1.197.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71B633F721; Tue, 2 Apr 2019 09:08:20 -0700 (PDT) Date: Tue, 2 Apr 2019 17:08:14 +0100 From: Lorenzo Pieralisi To: Bharat Kumar Gogada Cc: "bhelgaas@google.com" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming Message-ID: <20190402160814.GA30068@e107981-ln.cambridge.arm.com> References: <1552304759-5394-1-git-send-email-bharat.kumar.gogada@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 01, 2019 at 05:00:40PM +0000, Bharat Kumar Gogada wrote: > Hi All, > > Please let me know if anyone has any inputs on this. > > Regards, > Bharat > > > > The current Multi MSI data programming fails if multiple end points > > requesting MSI and multi MSI are connected with switch, i.e the current > > multi MSI data being given is not considering the number of vectors being > > requested in case of multi MSI. > > Due to this if multiple end points are connected and requesting MSI and > > multi MSI combination, the multi MSI data is ending up using wrong MSI > > data, which might be used by different device. > > > > Fix Multi MSI data programming with required alignment by using number > > of vectors being requested. I still do not understand what you mean I am sorry. An example is worth two thousand words, I would start with that as it stands this commit log does not provide any information on what you are actually fixing. Lorenzo > > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host > > Controller") > > Signed-off-by: Bharat Kumar Gogada > > --- > > V2: > > - Added more description of fix > > --- > > drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c > > b/drivers/pci/controller/pcie-xilinx-nwl.c > > index 81538d7..36669c5 100644 > > --- a/drivers/pci/controller/pcie-xilinx-nwl.c > > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c > > @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain > > *domain, unsigned int virq, > > > > mutex_lock(&msi->lock); > > bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0, > > - nr_irqs, 0); > > + nr_irqs, nr_irqs - 1); > > if (bit >= INT_PCI_MSI_NR) { > > mutex_unlock(&msi->lock); > > return -ENOSPC; > > -- > > 2.7.4 >