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[209.132.180.67]) by mx.google.com with ESMTP id q88si12563561pfa.222.2019.04.02.19.37.52; Tue, 02 Apr 2019 19:38:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=ZIxYoi8R; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726089AbfDCCg4 (ORCPT + 99 others); Tue, 2 Apr 2019 22:36:56 -0400 Received: from mail-oi1-f194.google.com ([209.85.167.194]:44686 "EHLO mail-oi1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726890AbfDCCgy (ORCPT ); Tue, 2 Apr 2019 22:36:54 -0400 Received: by mail-oi1-f194.google.com with SMTP id i21so12281793oib.11 for ; Tue, 02 Apr 2019 19:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yclw0WY4SjlZ13NhfTcy8gAGVQqxZafa6XnGdXkfYEI=; b=ZIxYoi8RF212CiSbiX/gsfNkaI/Zle1KnDJOW7VOaX5H3OK/+IVYDeMPVQRTCU/zW/ AsPo7cXv/yRe12CBgTWFyPHOdN3WG+qjYFq0sUgmrrEifhlXH27MiLLBRRK3JyFcvBPZ tE9eEMNZSJYXAbR91CwqQxcxLz9QDCMOualugTqRXjAIGELgqpMxJbZx5uiIl+DT2BMa wdoCday1C1c8tp/Ws5I11cGWzNz9KEdVZXCklDWZw8WqbZ6Ytq+mxP4OaCaeiawj+vVc kYoQ/M6G5ngOqNt1xqHEdpyI98by9LqEIgS/Sj3jyUJdosThB5K/aHhXhF06Rvm3KJBk fgiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yclw0WY4SjlZ13NhfTcy8gAGVQqxZafa6XnGdXkfYEI=; b=oocfKuyGtfOqh2HX1v+Hlsf4J7g8pftMEsat5Vrj+KKeJWpPQylXaeKoV8gMGYnrEi vjYQvi5QthTrnP7/Tujb4iLlvL1uR14p1L8OeNFeK7wGIdT7jOjfFLhknndex5D0SgVs bWKNE06D/3KKv7QKYiNLOxsHiDFnfXbf/N85U7DqOF8QXTmQ/yPeSfaq/uWkVCdRBdnJ c4gniLN4/0r6vywoTYMmeI4S6TU41d4yYnsLSeu//RTkeKdA97y5K5H8BBqXfk83c120 rX09rzRDZ4fDzKmMvyGJm7t8q2KmdAzjLDsOJlLJ42BZPN+bY7LAF4jIbmKY7qNVXCok dRAw== X-Gm-Message-State: APjAAAV2cCGP+BjUxkVQ2AwgobZVrd+i/0Tl1UJdH81kroTBnsgFpuSL a+ITlgnAtUnhhNgJefeYHj4B7Dno6nUQOcwizHg= X-Received: by 2002:aca:f1d4:: with SMTP id p203mr166219oih.154.1554259013877; Tue, 02 Apr 2019 19:36:53 -0700 (PDT) MIME-Version: 1.0 References: <1437124312-44700-1-git-send-email-b18965@freescale.com> <20151027081834.GB1425@svinekod> <4875455.lvoc6XpkZc@wuerfel> <20160102102955.GP8644@n2100.arm.linux.org.uk> In-Reply-To: From: Yang Li Date: Tue, 2 Apr 2019 21:36:42 -0500 Message-ID: Subject: Re: [PATCH] arm: kernel: utilize hrtimer based broadcast To: Thomas Gleixner Cc: Russell King - ARM Linux , "mark.rutland@arm.com" , Daniel Lezcano , Arnd Bergmann , Huan Wang , Huan Wang , "linux-kernel@vger.kernel.org" , John Stultz , LAK Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 5, 2016 at 3:46 AM Thomas Gleixner wrote: > > On Sat, 2 Jan 2016, Russell King - ARM Linux wrote: > > On Tue, Dec 29, 2015 at 02:54:10PM +0100, Thomas Gleixner wrote: > > > I have no real opinion about that patch. It does no harm to unconditionally > > > setup the hrtimer based broadcast even if it's never used. > > > > > > Up to the arch maintainer to decide. > > > > That's really not fair to keep shovelling these kinds of decisions onto > > architecture maintainers without any kind of explanation about how an > > architecture maintainer should make such a decision. > > > > Do I roll a 6-face dice, and if it gives an odd number, I apply this > > patch, otherwise I reject it? > > > > Is there a technical basis for making the decision? If so, please > > explain what the technical arguments are against having or not having > > this change. > > The hrtimer based broadcast device is used when you have per cpu timers which > stop in deeper power states, but you have no other timer hardware on the chip > which can backup the per cpu timer in deep power states. The trick is that it > emulates a timer hardware via a hrtimer and then tells the cpu idle code not > to go into deep power states on the cpu which owns that hrtimer. All other > cpus can go as deep as they want and still get woken up. > > The only downside of adding this unconditionally is extra code in case that it > is not needed on a particular platform. > > Hope that helps. Hi Russell, This has been pending for so long time. I assume this is an ack from Thomas. And given the same thing has been added for arm64 and powerpc architecture, can you also merge this for ARM? Regards, Leo