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[209.132.180.67]) by mx.google.com with ESMTP id l62si4781576pge.579.2019.04.03.01.18.04; Wed, 03 Apr 2019 01:18:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728938AbfDCIRO (ORCPT + 99 others); Wed, 3 Apr 2019 04:17:14 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:32644 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726862AbfDCIQ7 (ORCPT ); Wed, 3 Apr 2019 04:16:59 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3386TVb004193; Wed, 3 Apr 2019 10:16:44 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2rmgev2kfg-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 03 Apr 2019 10:16:44 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6F76034; Wed, 3 Apr 2019 08:16:43 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 533B0146C; Wed, 3 Apr 2019 08:16:43 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.435.0; Wed, 3 Apr 2019 10:16:43 +0200 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.435.0; Wed, 3 Apr 2019 10:16:42 +0200 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , David Airlie , Daniel Vetter , Rob Herring , "Mark Rutland" , Maxime Coquelin , Alexandre Torgue , , , , , Subject: [PATCH v1 3/5] ARM: dts: stm32: add phy-dsi-supply property on stm32mp157c Date: Wed, 3 Apr 2019 10:16:27 +0200 Message-ID: <1554279389-27377-4-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554279389-27377-1-git-send-email-yannick.fertre@st.com> References: <1554279389-27377-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-03_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dsi physical layer is powered by the 1v8 power controller supply. Signed-off-by: Yannick Fertré --- arch/arm/boot/dts/stm32mp157c.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 6ce75f6..4611b57 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1143,6 +1143,7 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; + phy-dsi-supply = <®18>; status = "disabled"; }; -- 2.7.4