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Subject: Re: [PATCH 1/2] stmmac: introduce flag to dynamically disable TX
 offload for rockchip devices
To:     "Leonidas P. Papadakos" <papadakospan@gmail.com>,
        Jose Abreu <jose.abreu@synopsys.com>
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        Alexandre Torgue <alexandre.torgue@st.com>,
        netdev@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Klaus Goger <klaus.goger@theobroma-systems.com>
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From:   Robin Murphy <robin.murphy@arm.com>
Message-ID: <c863f88a-65e2-4093-7cc1-f37e4443b871@arm.com>
Date:   Wed, 3 Apr 2019 17:12:03 +0100
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On 03/04/2019 16:55, Leonidas P. Papadakos wrote:
> 
>> If snps,no-pbl-x8 does indeed have a performace hit, should the 
>> workaround be to
>> a) turn tx checksumming off or
>> b) snps,no-pbl-x8 set?
>>
>> I'll test to see the difference
> 
> Update: It really seems like snps,no-pbl-x8 is the better option.
> So I say, replace snps,force_thresh_dma_mode with it.

Yes, I would expect software checksumming to have a much more noticeable 
impact (in fact I've already been trying to get round to benchmarking 
some arm64 checksum optimisations on my RK3328 precisely because of this 
issue).

If I'm interpreting the register descriptions in the Rockchip TRMs 
correctly, it seems like no-pbl-x8 is a relatively big hammer and there 
should still be room to tune things a bit closer to the maximum limits - 
I'll have another play this evening to see if I've understood things right.

Robin.