Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp564382yba; Wed, 3 Apr 2019 14:32:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1CzqPaaYIxuahpV5yvIuwuk9jhp7j94M/4PZnrufjvKmEvrQ1OuvHepNn0r+qHEXl0Ft7 X-Received: by 2002:a63:d256:: with SMTP id t22mr1927860pgi.80.1554327153794; Wed, 03 Apr 2019 14:32:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554327153; cv=none; d=google.com; s=arc-20160816; b=Sl8HBVwUIJf3skK8dha2dZripsbSpghyJbY8fN0qlqM5CGyS3quBreVIUszMAoHw4t Keb3Po3yj3YInodY01ec4EqIVh3Vr+tVWvlFz4K3K2KifbphbpmS6hfSB92JbWDQ40k6 V1q99uCZk80f6URpgNmqyriYe/G2QZD7/d5ng0cpCR2I9AT9oL5yuo2gh/nw9q+2Xwms ggbLoPTxW7KaYK0DbFYIoTcbHpIV5uC2ScEsabw0+FR5gOy5vxu5LV9ctbs3fwa+N8k3 Nxp4BJkPjkhPHyX1oBJcxcHko/mn+0b0Prr/OKKCw7Xmpl22ufMmSS876Poj0F38whiP VLpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=5VMd54M3mWD/j0sqieeZ/GxOZIT89sy7GN8j5SGRfcs=; b=ZreuQtIQyscPYJ+D514wHV+y8dvwc0INHy34MQAiolLu4+0UTIX357yVjRe73EjTD8 lhPraf/+g10fHsxMweo4bEGbwjoxjHSHyrTSSseUJsp/Q3/9Hsspg5Th60Ad+NkkS6C6 mEIMEo2UorQ4pabe0tDAGDh7bZGxZXav3XYjQyTioyXPlcNSjkXCYMLtVOkMTODHWsG5 sJixV5cpq8HSehzM7sCasoSoGDo85LPV97/hHX24Ckm6fxJDTurA4dFuzzMrrtWGcuPU b2FvKyah54m1jWFZGzqGzp+AwYz8TCIo9JhMvok9na9KLwEYyhF/f2kQxi3qdck3gjD6 FJLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w70si10719319pgd.571.2019.04.03.14.32.18; Wed, 03 Apr 2019 14:32:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728046AbfDCVbF (ORCPT + 99 others); Wed, 3 Apr 2019 17:31:05 -0400 Received: from mga05.intel.com ([192.55.52.43]:37323 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726785AbfDCVaV (ORCPT ); Wed, 3 Apr 2019 17:30:21 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2019 14:30:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,306,1549958400"; d="scan'208";a="334754246" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 14:30:11 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Dave Hansen" , "Paolo Bonzini" , "Ashok Raj" , "Peter Zijlstra" , "Kalle Valo" , "Xiaoyao Li " , "Michael Chan" , "Ravi V Shankar" Cc: "linux-kernel" , "x86" , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, kvm@vger.kernel.org, Fenghua Yu Subject: [PATCH v6 09/20] x86/split_lock: Define MSR_TEST_CTL register Date: Wed, 3 Apr 2019 14:21:55 -0700 Message-Id: <1554326526-172295-10-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> References: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setting bit 29 in MSR_TEST_CTL register 0x33 enables split lock detection and clearing the bit disables split lock detection. Define the MSR and the bit. The definitions will be used in enabling or disabling split lock detection. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f65ef6f783d2..25fa808de9e2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,10 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_TEST_CTL 0x00000033 +#define TEST_CTL_ENABLE_SPLIT_LOCK_DETECT_SHIFT 29 +#define TEST_CTL_ENABLE_SPLIT_LOCK_DETECT BIT(29) + #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ -- 2.19.1