Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp566035yba; Wed, 3 Apr 2019 14:34:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqzCJETHaNIvdM1fScGh6Ptiz9uKMP8jIyieuJfx/ZnqMoozO5HBpAuIAAIC/SJYzs78t1X4 X-Received: by 2002:a17:902:1029:: with SMTP id b38mr2402457pla.204.1554327285768; Wed, 03 Apr 2019 14:34:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554327285; cv=none; d=google.com; s=arc-20160816; b=yK6m2MmJQ+4p23hhAV1ok/CPN8VY9Nk0T/E8rr360fYMg2hY1+mamVww5HZiCQVTgl oYAzMjT39H/OwWbpFoBPh3ObGLDhMxPirt3ZMSOHKtvFy1XCrQrHJAVRYofPfS5KiT13 x/ZNB/PfymNH49WKyBZqBHay2uGlnG/64GV5Jp2GNydJUJzjaiu2FuL9YpIwH40Q9DyK BKT+EgVot9h3GmeJdd6pbUYYYJdxDYVMRuiEbIp17JdS/m2DB7tmuTzwUReHrLp/h6Q+ QquvwppdOiRvJ33ZPyY1yJqCr+RJAq3H5IS+WPkGBPMFbDzXDLZkiLKkHhXu8toLtclx dnBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=vr5U12baX0E6DOH9f4SwhxIh3bDHr4RLerkNESYXPFw=; b=ve//5P5d441RGY42kJWjzS5dqN313b+Oz3M1hb2a05e6wDJF6yTGFQi5SiOwdEwtER hoTEepOUmucAkkiGg9rSqi10AP0MgVE9W+14sAQbqVduRabLO6pnT4qUvz/ng42CJnRW M12D9v/SANUJlsBtpdpUVnYhamMbB5QsD4Kb6RCvOVBEktnEIZFmC8cnZkb5F2Sj2BX7 x26p+leDBrsa/z3gcnPM3kXKSynSOTAQRQh78rs5ebVA8kkqRLan+sqIoL3JBbAUiqdg KLbfWRFEu8Lt62aVJdAR0Wq/ZjiL3UshjySiXsyqbMYDDBwRY8gD8IYq6Aqq950JWfuf kKpg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x4si14679003plo.203.2019.04.03.14.34.30; Wed, 03 Apr 2019 14:34:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728671AbfDCVcL (ORCPT + 99 others); Wed, 3 Apr 2019 17:32:11 -0400 Received: from mga05.intel.com ([192.55.52.43]:37323 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726711AbfDCVaU (ORCPT ); Wed, 3 Apr 2019 17:30:20 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2019 14:30:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,306,1549958400"; d="scan'208";a="334754232" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 14:30:10 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Dave Hansen" , "Paolo Bonzini" , "Ashok Raj" , "Peter Zijlstra" , "Kalle Valo" , "Xiaoyao Li " , "Michael Chan" , "Ravi V Shankar" Cc: "linux-kernel" , "x86" , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, kvm@vger.kernel.org, Fenghua Yu Subject: [PATCH v6 02/20] drivers/net/b44: Align pwol_mask to unsigned long for better performance Date: Wed, 3 Apr 2019 14:21:48 -0700 Message-Id: <1554326526-172295-3-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> References: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peter Zijlstra A bit in pwol_mask is set in b44_magic_pattern by atomic set_bit. But since pwol_mask is local and never exposed to concurrency, there is no need to set bit in pwol_mask atomically. set_bit sets the bit in a single unsigned long location. Because pwol_mask may not be aligned to unsigned long, the location may cross two cache lines. On x86, accessing two cache lines in locked instruction in set_bit is called split lock and can cause overall performance degradation. So use non atomic __set_bit to set pwol_mask bits. __set_bit won't hit split lock issue on x86. Signed-off-by: Peter Zijlstra Signed-off-by: Fenghua Yu --- drivers/net/ethernet/broadcom/b44.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c index 97ab0dd25552..5738ab963dfb 100644 --- a/drivers/net/ethernet/broadcom/b44.c +++ b/drivers/net/ethernet/broadcom/b44.c @@ -1520,7 +1520,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset) memset(ppattern + offset, 0xff, magicsync); for (j = 0; j < magicsync; j++) - set_bit(len++, (unsigned long *) pmask); + __set_bit(len++, (unsigned long *)pmask); for (j = 0; j < B44_MAX_PATTERNS; j++) { if ((B44_PATTERN_SIZE - len) >= ETH_ALEN) @@ -1532,7 +1532,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset) for (k = 0; k< ethaddr_bytes; k++) { ppattern[offset + magicsync + (j * ETH_ALEN) + k] = macaddr[k]; - set_bit(len++, (unsigned long *) pmask); + __set_bit(len++, (unsigned long *)pmask); } } return len - 1; -- 2.19.1