Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp1378311yba; Thu, 4 Apr 2019 09:32:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqyO1dSH6QaXXtjY/GDFB1GwI/fknCMuXLaa29CQBRrQCC0SYup6L77eq442uoBuJxd5umW2 X-Received: by 2002:a63:465b:: with SMTP id v27mr6930739pgk.165.1554395578541; Thu, 04 Apr 2019 09:32:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554395578; cv=none; d=google.com; s=arc-20160816; b=oES3X2a7TrAd3KYFaQHACBdXwbYf98VLyMW1SXlRNLNluh2C1OTl+uFQZFjTSZPoDf Z3v+jFIbsqfjbiKds+nkh5wWZgr+q4zh01MBfIih+OgAHK3PcjNCipM5bqq84o+vfRdT rBoUE0mHzKl4EVxdThrWxvZs2DEg3z0eAMp3ARiIoRtjzWGwkwXGqNDQRBztk07ESsCp RfOX1Udxb54ndz3Mjz3G69KeVqTt7GfP2502MYHebzGeoYw4rVdCMVk70owxVAhLi+fm UKZquwRqk3GVm1/9SvZXTIOMG8GOMYJL+SxxqegiXzPE0+PzZBFTvqVaGtEhUXoAdsUU OvHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from; bh=AccGVhAZdh9xEdX5hp0G11TVhuRvGSsV46mmp42nYTM=; b=a5wTf3NjyMnwD+wzh03W1uC+kd3+JssSdta11GrtXJ1oPrb5SWrS1gjOdqnyYHfXxl F0ErYvHdM11nzTmN7dz6g1QLFIryDDqeGN/zkcGJNSOb1J0t2RVB6WHb/LA7NQxSxfdU cWuDdEX7Z114hYBcPOEySj2TBdxrIwo3dCidGssa6eONeagHQafFa5oe6NZmkm5J9mVn dxMvgCU9MoPhCxsV2ORKJkPpWBvf2iCZtoq3VPcn/FMvMojmzf2yN6IFsMyztpEr+7BG ZKJn0Gjg3r/3j0oeKSBFaaErCB1awZvQFBOdAx35muUDvtuOfMaKcWYJ0kKhooLtwsvy 9t8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a18si17012160pgk.464.2019.04.04.09.32.42; Thu, 04 Apr 2019 09:32:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729186AbfDDQcF convert rfc822-to-8bit (ORCPT + 99 others); Thu, 4 Apr 2019 12:32:05 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:32918 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727053AbfDDQcE (ORCPT ); Thu, 4 Apr 2019 12:32:04 -0400 Received: from LHREML712-CAH.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 6070DFF7FF970DE39579; Thu, 4 Apr 2019 17:32:03 +0100 (IST) Received: from LHREML524-MBS.china.huawei.com ([169.254.2.229]) by LHREML712-CAH.china.huawei.com ([10.201.108.35]) with mapi id 14.03.0415.000; Thu, 4 Apr 2019 17:31:55 +0100 From: Shameerali Kolothum Thodi To: Will Deacon CC: "lorenzo.pieralisi@arm.com" , "robin.murphy@arm.com" , "andrew.murray@arm.com" , "jean-philippe.brucker@arm.com" , "mark.rutland@arm.com" , "Guohanjun (Hanjun Guo)" , "John Garry" , "pabba@codeaurora.org" , "vkilari@codeaurora.org" , "rruigrok@codeaurora.org" , "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linuxarm , "neil.m.leeder@gmail.com" Subject: RE: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Topic: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Index: AQHU4+eNGDYznP+LJkGbBgcrT5VMl6YsIsKAgAAVvUA= Date: Thu, 4 Apr 2019 16:31:55 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8393575FC@lhreml524-mbs.china.huawei.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> <20190404154711.GA27577@fuggles.cambridge.arm.com> In-Reply-To: <20190404154711.GA27577@fuggles.cambridge.arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: 04 April 2019 16:47 > To: Shameerali Kolothum Thodi > Cc: lorenzo.pieralisi@arm.com; robin.murphy@arm.com; > andrew.murray@arm.com; jean-philippe.brucker@arm.com; > mark.rutland@arm.com; Guohanjun (Hanjun Guo) ; > John Garry ; pabba@codeaurora.org; > vkilari@codeaurora.org; rruigrok@codeaurora.org; linux-acpi@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Linuxarm > ; neil.m.leeder@gmail.com > Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 > quirk > > On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > > HiSilicon erratum 162001800 describes the limitation of > > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > > > On these platforms, the PMCG event counter registers > > (SMMU_PMCG_EVCNTRn) are read only and as a result it > > is not possible to set the initial counter period value > > on event monitor start. > > > > To work around this, the current value of the counter > > is read and used for delta calculations. OEM information > > from ACPI header is used to identify the affected hardware > > platforms. > > > > Signed-off-by: Shameer Kolothum > > Reviewed-by: Hanjun Guo > > Reviewed-by: Robin Murphy > > --- > > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > > drivers/perf/arm_smmuv3_pmu.c | 48 > ++++++++++++++++++++++++++++++++++++------- > > include/linux/acpi_iort.h | 1 + > > 3 files changed, 57 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index e2c9b26..4dc68de 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -1366,9 +1366,23 @@ static void __init > arm_smmu_v3_pmcg_init_resources(struct resource *res, > > ACPI_EDGE_SENSITIVE, &res[2]); > > } > > > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > > + /* HiSilicon Hip08 Platform */ > > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, > > Passing integer constant 0 for the reason feels wrong to me. I'm going to > change it to "Erratum #162001800" and also add an entry to > silicon-errata.txt. > > Please shout if that's not ok. Thanks Will for taking a look at this series. The proposed changes are fine to me. Shameer