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[209.132.180.67]) by mx.google.com with ESMTP id 16si18068999pfr.26.2019.04.04.21.14.57; Thu, 04 Apr 2019 21:15:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b="Tx+GE/ky"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726467AbfDEEOP (ORCPT + 99 others); Fri, 5 Apr 2019 00:14:15 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:38845 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726027AbfDEEOP (ORCPT ); Fri, 5 Apr 2019 00:14:15 -0400 Received: by mail-wm1-f68.google.com with SMTP id w15so5636558wmc.3 for ; Thu, 04 Apr 2019 21:14:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=mBHVrWRKGZevbfTKeXKRxI9gf6sJ5d1z7tzrVixC8Jk=; b=Tx+GE/kyMVuyulYFD856bWPolojQWzZWKuGBYAyKjK0wSk4YRKTXZo6o4ZTOpJgsos XQLvCcklGLmb66PPfiTWzUIWKIvNAVr6bC4EK1694Bit61uQlb1nNs67L+xwuxdl+PdX h4ivnwEstWB2XAVo/kCN4+ygPl9oCOa/pI2nucctjYQjixoE9p2B2NieLcCvq/smEOzv TWdJ2OrpLVzl1UGmcl93EOStMTOnOap/+WLoODhnByD6uG4l10NgxaH2EN6fKYZwp6i0 DCLg5XXKc7J3QjtjAUdqw6/870X0w+b8BWvDHsIQYMwDs6d1as/suV81ZZ8FMq7MVqoA PVvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mBHVrWRKGZevbfTKeXKRxI9gf6sJ5d1z7tzrVixC8Jk=; b=GFSeHd8pO9rTHLjfK9YSQlhxgaYSaBr1cl/f38Z5yWKZ17djqR+dD36735kwyJagLj 5dOk4y/ny7EraZJ8zsHEXLBiZAauzi8yyh1p7NqAm84FsBsgaDqhl+Zt4W0ypdqZ9ui4 xpm+4GrL9HliSbpZOPUpQoSuveiQV70BznkqTYLqqnHYP3/mE5vmI+R6wDXs78iA9nhL de4aOzoqQXLzVaXXdlrsRB2+C9lQNvOZupY/w7yUzDBMInXcPxOhNhvGdZSQhkW7MsoX XGEkE4EvgNB3yEm9tW2TaoVGOMXH6SuhK/YLx5VjsHTcKOdpO4eNMGDxsCTiRWGFT5MQ UEKg== X-Gm-Message-State: APjAAAVLYf2M5yLbIyRBC4roRDhFHJT54WXRrbJlr9jqFxQoN7upEjwR XPYDAARMCBNmZ3EflUy37wYf5q6uRQQfvgKpZ9Z/Pw== X-Received: by 2002:a1c:1f08:: with SMTP id f8mr5700645wmf.97.1554437653482; Thu, 04 Apr 2019 21:14:13 -0700 (PDT) MIME-Version: 1.0 References: <20190403141627.11664-1-steven.price@arm.com> <20190403141627.11664-7-steven.price@arm.com> In-Reply-To: <20190403141627.11664-7-steven.price@arm.com> From: Anup Patel Date: Fri, 5 Apr 2019 09:44:02 +0530 Message-ID: Subject: Re: [PATCH v8 06/20] riscv: mm: Add p?d_large() definitions To: Steven Price Cc: linux-mm@kvack.org, Andy Lutomirski , Ard Biesheuvel , Arnd Bergmann , Borislav Petkov , Catalin Marinas , Dave Hansen , Ingo Molnar , James Morse , =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , Peter Zijlstra , Thomas Gleixner , Will Deacon , x86@kernel.org, "H. Peter Anvin" , linux-arm-kernel , "linux-kernel@vger.kernel.org List" , Mark Rutland , "Liang, Kan" , Andrew Morton , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 3, 2019 at 7:47 PM Steven Price wrote: > > walk_page_range() is going to be allowed to walk page tables other than > those of user space. For this it needs to know when it has reached a > 'leaf' entry in the page tables. This information is provided by the > p?d_large() functions/macros. > > For riscv a page is large when it has a read, write or execute bit > set on it. > > CC: Palmer Dabbelt > CC: Albert Ou > CC: linux-riscv@lists.infradead.org > Signed-off-by: Steven Price > --- > arch/riscv/include/asm/pgtable-64.h | 7 +++++++ > arch/riscv/include/asm/pgtable.h | 7 +++++++ > 2 files changed, 14 insertions(+) > > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h > index 7aa0ea9bd8bb..73747d9d7c66 100644 > --- a/arch/riscv/include/asm/pgtable-64.h > +++ b/arch/riscv/include/asm/pgtable-64.h > @@ -51,6 +51,13 @@ static inline int pud_bad(pud_t pud) > return !pud_present(pud); > } > > +#define pud_large pud_large > +static inline int pud_large(pud_t pud) > +{ > + return pud_present(pud) > + && (pud_val(pud) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); > +} > + > static inline void set_pud(pud_t *pudp, pud_t pud) > { > *pudp = pud; > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 1141364d990e..9570883c79e7 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -111,6 +111,13 @@ static inline int pmd_bad(pmd_t pmd) > return !pmd_present(pmd); > } > > +#define pmd_large pmd_large > +static inline int pmd_large(pmd_t pmd) > +{ > + return pmd_present(pmd) > + && (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); > +} > + > static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) > { > *pmdp = pmd; > -- > 2.20.1 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup