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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id 17sm40141650pgz.52.2019.04.08.03.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Apr 2019 03:40:56 -0700 (PDT) From: You-Sheng Yang To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Pavel Tatashin , Peter Zijlstra , "Rafael J. Wysocki" , Dou Liyang , Daniel Vacek , Mike Travis , Xiaoming Gao Cc: You-Sheng Yang , "H. Peter Anvin" , Chuanhua Lei , Juergen Gross , linux-kernel@vger.kernel.org Subject: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake Date: Mon, 8 Apr 2019 18:40:10 +0800 Message-Id: <20190408104012.26791-1-vicamo@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: You-Sheng Yang On Intel CoffeeLake it's observed tsc is always marked unstable unexpectedly after entering idle state Package C10(PC10), and then clock source is switched to hpet. This patch marks tsc as reliable when CPUID matches CoffeeLake. Link: https://bugzilla.kernel.org/show_bug.cgi?id=203183 Signed-off-by: You-Sheng Yang --- arch/x86/kernel/tsc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index aab0c82e0a0d..2abbadc9cff0 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1161,6 +1161,16 @@ static void __init check_system_tsc_reliable(void) #endif if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) tsc_clocksource_reliable = 1; + + /* + * On Intel CoffeeLake, tsc may be marked unstable unexpectedly after + * entering PC10. + */ + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + (boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_MOBILE || + boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_DESKTOP) && + boot_cpu_data.x86_stepping >= 0x0a) + tsc_clocksource_reliable = 1; } /* -- 2.20.1