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Date:   Mon, 8 Apr 2019 14:03:36 +0200 (CEST)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     You-Sheng Yang <vicamo@gmail.com>
cc:     Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        x86@kernel.org, Pavel Tatashin <pasha.tatashin@oracle.com>,
        Peter Zijlstra <peterz@infradead.org>,
        "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
        Dou Liyang <douly.fnst@cn.fujitsu.com>,
        Daniel Vacek <neelx@redhat.com>,
        Mike Travis <mike.travis@hpe.com>,
        Xiaoming Gao <gxm.linux.kernel@gmail.com>,
        You-Sheng Yang <vicamo.yang@canonical.com>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Chuanhua Lei <chuanhua.lei@linux.intel.com>,
        Juergen Gross <jgross@suse.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake
In-Reply-To: <20190408104012.26791-1-vicamo@gmail.com>
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References: <20190408104012.26791-1-vicamo@gmail.com>
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On Mon, 8 Apr 2019, You-Sheng Yang wrote:

> From: You-Sheng Yang <vicamo.yang@canonical.com>
> 
> On Intel CoffeeLake it's observed tsc is always marked unstable
> unexpectedly after entering idle state Package C10(PC10), and then clock
> source is switched to hpet. This patch marks tsc as reliable when CPUID
> matches CoffeeLake.

This lacks a proper analysis:

  1) Why is it marked unstable

  2) Why is it correct to set that for coffeelake
 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=203183
> Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
> ---
>  arch/x86/kernel/tsc.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
> index aab0c82e0a0d..2abbadc9cff0 100644
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -1161,6 +1161,16 @@ static void __init check_system_tsc_reliable(void)
>  #endif
>  	if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
>  		tsc_clocksource_reliable = 1;
> +
> +	/*
> +	 * On Intel CoffeeLake, tsc may be marked unstable unexpectedly after
> +	 * entering PC10.
> +	 */
> +	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> +	    (boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_MOBILE ||
> +	     boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_DESKTOP) &&
> +	    boot_cpu_data.x86_stepping >= 0x0a)
> +		tsc_clocksource_reliable = 1;

No. We are not starting that family/model/stepping game especially not
with random stepping cutoffs which are pulled out of thin air.  That's
going to spiral out of control sooner than later.

There must be a better way to do that. Rafael?

Thanks,

	tglx