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[209.85.166.178]) by smtp.gmail.com with ESMTPSA id y24sm11412111iol.8.2019.04.08.11.14.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Apr 2019 11:14:31 -0700 (PDT) Received: by mail-it1-f178.google.com with SMTP id q14so662683itk.0 for ; Mon, 08 Apr 2019 11:14:31 -0700 (PDT) X-Received: by 2002:a24:298b:: with SMTP id p133mr22379438itp.81.1554746949463; Mon, 08 Apr 2019 11:09:09 -0700 (PDT) MIME-Version: 1.0 References: <20190131192533.34130-1-thgarnie@chromium.org> <20190131192533.34130-15-thgarnie@chromium.org> <01000168a5b35a86-b79bfe67-191e-43bc-a5c7-0e74eac06195-000000@email.amazonses.com> <01000168a6e5ab88-0deea73f-387f-4941-bd11-d1c161aac88a-000000@email.amazonses.com> <01000169fe18026e-a0951268-516c-4604-a4c3-140f3cbb6f7a-000000@email.amazonses.com> In-Reply-To: <01000169fe18026e-a0951268-516c-4604-a4c3-140f3cbb6f7a-000000@email.amazonses.com> From: Thomas Garnier Date: Mon, 8 Apr 2019 11:08:58 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 14/27] x86/percpu: Adapt percpu for PIE support To: Christopher Lameter Cc: Kernel Hardening , Kristen Carlson Accardi , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "the arch/x86 maintainers" , Dennis Zhou , Tejun Heo , Boris Ostrovsky , Juergen Gross , Stefano Stabellini , Andrew Morton , Andi Kleen , "Kirill A. Shutemov" , Michal Hocko , Mike Rapoport , Stephen Rothwell , Cao jin , Brijesh Singh , Masahiro Yamada , Joerg Roedel , Peter Zijlstra , Kees Cook , Mathieu Desnoyers , LKML , xen-devel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 8, 2019 at 10:56 AM Christopher Lameter wrote: > > On Mon, 8 Apr 2019, Thomas Garnier wrote: > > > > It didn't work originally but I will revisit to see if I missed something. > > > > I revisited and couldn't find a way to prevent relocations to the > > percpu section. Without PIE, you can reference absolute address which > > was convenient for percpu. > > Can you switch PIE off for the percpu section? If not maybe the linker > needs to have an additional option? I don't think so or I didn't find any option to do that. Changing the linker might be a bit too much if we have a software solution which doesn't impact performance. > > Cannot imagine that this is not possible. You neeed to be able to > reference registers that are in fixed memory locations. > > > > Christopher: Did you have something specific in mind? > > I thought that we just leave it as is. I would like to as well. I will try couple things at the assembly level instead of the linker and come back to this thread.