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[209.132.180.67]) by mx.google.com with ESMTP id q18si26726799pls.319.2019.04.09.09.05.30; Tue, 09 Apr 2019 09:05:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=hanoverdisplays.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726592AbfDIQEg (ORCPT + 99 others); Tue, 9 Apr 2019 12:04:36 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:54055 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726383AbfDIQEg (ORCPT ); Tue, 9 Apr 2019 12:04:36 -0400 Received: by mail-wm1-f66.google.com with SMTP id q16so4233569wmj.3; Tue, 09 Apr 2019 09:04:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NWwbBuZC+XjhAuW0RZ7Nu80M8IGtTFgC21+5MwcriIE=; b=pgyUOFJaBVpb5nZUrHxCALWl2BbWJoNRBn35OIDRR6fYQKapvgt9N579eZaDE8rKsA hs1A4nY1SajAS8rBm+rC7lFVAVfV19XfCae6voaG9oGS79aMogj4TazH0gsOHmm47L+S vVkDvSwPpdeIp01WsbMr9OqJhzv1QnkYqNJyocr4EV8DMtKsYf3QlSuQ7mRxP/YIUC8K PLNI8zf6sf9xGLbH+I4lwR7gFL9Q30xlLeFsnu0Y0fciAXgHSpZY+CWmo+VaSJh8o4c9 RVRQGy7XdREcjF924lb5HT1NgAhMZOXiGKAqbQbZMBBi5GVXBIM9IIT1+Ii46THX9Zb1 yHrw== X-Gm-Message-State: APjAAAUqEN2tk8fBpgQ7NS0jdqIuppwxe6EiycssXqRInAVR7w1mIWSa hVHMYcgAth5wFixN0sVHeD8= X-Received: by 2002:a1c:230e:: with SMTP id j14mr23131236wmj.120.1554825874154; Tue, 09 Apr 2019 09:04:34 -0700 (PDT) Received: from localhost ([90.85.130.193]) by smtp.gmail.com with ESMTPSA id s189sm31430147wmf.45.2019.04.09.09.04.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Apr 2019 09:04:33 -0700 (PDT) From: Christina Quast To: tony@atomide.com Cc: Christina Quast , Benoit Cousson , Rob Herring , Mark Rutland , linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/15] ARM: dts: am335x: baltos-ir2110: Replaced register offsets with defines Date: Tue, 9 Apr 2019 18:03:32 +0200 Message-Id: <20190409160346.25599-2-cquast@hanoverdisplays.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190409160346.25599-1-cquast@hanoverdisplays.com> References: <20190409160346.25599-1-cquast@hanoverdisplays.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 75de1e723303..e5e10fa3cae2 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -23,14 +23,14 @@ &am33xx_pinmux { uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ >; }; }; -- 2.20.1