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[209.132.180.67]) by mx.google.com with ESMTP id q13si33993895pls.284.2019.04.11.06.33.22; Thu, 11 Apr 2019 06:33:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=poDHCcir; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726801AbfDKNcl (ORCPT + 99 others); Thu, 11 Apr 2019 09:32:41 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:40312 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726538AbfDKNcl (ORCPT ); Thu, 11 Apr 2019 09:32:41 -0400 Received: by mail-lf1-f67.google.com with SMTP id a28so4723409lfo.7 for ; Thu, 11 Apr 2019 06:32:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=xvSuYyh6IKBEj54FFCtw6W7UjqwtB1CXJsCRn+E+pGw=; b=poDHCcirbQv0Ydxb9B8Y0kJjroHTkglNGRX9V7PrXX5qAiDRxul61bGRvdreuA3vDm i5gSa/Hz2dz8DsZVroN7DbQe3PjnN31070Y+eNrQzZRKkhlWEdo6awG0XKknON79hMdX Gtzzdk0Aw5S2/vIA/yJcyEZbQqNI21hkhf4Hnhz/awT0kpJ/MeKwMHDOi/k5IkG5kMSP MNSzY9NKRo6u/HdOgjOQB0NkOcHHzi4OL4V92M6vJY28YWLjf3mu8lH97PQSpHevW42N r0UsvPf/+dAF3HF+jSXgjce3iqvzzcf0wSj9p1/2qqnPcz9Nnci5ba8W/EXWqGO3n3VS 33QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xvSuYyh6IKBEj54FFCtw6W7UjqwtB1CXJsCRn+E+pGw=; b=DN5IYsMmTlviTUk5k6sNg3csCvxZDQxgRBvxZUreevZB/rFZ2ASX9CNBusuxuOtlFV HVWPs1B9p7OJKOosRQvg3Afi2M5NYLj3tIYA/2QJaP6wB1PDDiU2dpohnhMT539YmVMz ANNEnD2L3yfALcCQfkAtNIrFU2FbJO388J6CW3IKB/b+/uqPHD+iTNn2p2KeRy+VNl5R wOTBTiTk9hHcL1L3ovBPGL0xXbOLIEtgOz4/Yc2d8nUqlUuqR1/xM011vsAWIHIsP8Gm YjPkat1HvaxoNCTKappKq+7ocZdRuf8KKTFOak7Tvsb1HIM5uQ8WZkvaZCCrBTCcGUcQ tqOw== X-Gm-Message-State: APjAAAVPcnPA5n7aRjqS5IWRKyq8L45pV6tivSYLaugs+NADfPAiW7+A WTd0c1esCH5fvC/RUIb1bQ3ZMDFQJs+eYmSHlkeV/w== X-Received: by 2002:ac2:546c:: with SMTP id e12mr15580332lfn.121.1554989559272; Thu, 11 Apr 2019 06:32:39 -0700 (PDT) MIME-Version: 1.0 References: <1554800820-5412-1-git-send-email-p.paillet@st.com> <1554800820-5412-3-git-send-email-p.paillet@st.com> In-Reply-To: <1554800820-5412-3-git-send-email-p.paillet@st.com> From: Linus Walleij Date: Thu, 11 Apr 2019 15:32:28 +0200 Message-ID: Subject: Re: [PATCH v2 2/3] ARM: dts: stm32: add stpmic1 support on stm32mp157a dk1 board To: Pascal PAILLET-LME Cc: "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux@armlinux.org.uk" , "horms+renesas@verge.net.au" , "olof@lixom.net" , "arnd@arndb.de" , "geert+renesas@glider.be" , "biju.das@bp.renesas.com" , Yannick FERTRE , "m.szyprowski@samsung.com" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 9, 2019 at 11:08 AM Pascal PAILLET-LME wrote: > This patch adds stpmic1 support on stm32mp157a dk1 board. > The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 > regulators, 3 power switches, a watchdog and an input for a power on key. > The DMAs are disabled because the PMIC generates a very few traffic and > DMA channels may lack for other usage. > > Signed-off-by: Pascal Paillet Reviewed-by: Linus Walleij Yours, Linus Walleij