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[209.132.180.67]) by mx.google.com with ESMTP id b68si17606871plb.351.2019.04.11.06.35.02; Thu, 11 Apr 2019 06:35:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p3wa8NUP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfDKNdQ (ORCPT + 99 others); Thu, 11 Apr 2019 09:33:16 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:32904 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726538AbfDKNdP (ORCPT ); Thu, 11 Apr 2019 09:33:15 -0400 Received: by mail-lj1-f193.google.com with SMTP id f23so5577415ljc.0 for ; Thu, 11 Apr 2019 06:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=laaJz8EQ2TImpAAiwiHz+eFnv5QTGyYOBMFay+FlkLU=; b=p3wa8NUPMarRp0Xb2D29Hex+wGEZAW3C1yDfGrIGCAfzN/g0sYRjFLxnyTzDWNBiUG iqQIkiUvdGi82YSwk8NG6eYroBFVkChGDCFfwbxnQ0yIUIgQCjTHGKC7AaUrsEE4Osc+ lDawUVtkiYEAAQ1838z7b86k7GdOelCnzCoH5ckqaSoCBFoH63xtTMLOzXxLN8nBhkbK Gfe03aqeFk0PqlLEP9+NMmsO0QCU6OyaqsAINyJm3XdmfxOuoYbjVkJdW2xXsEWCm7I5 Md2lam+UKabdSamJKeqNjTN5/2L6AwXYC73iKOVGfDK1TAUzqdizyWfobb6oUl4LSpdi QuXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=laaJz8EQ2TImpAAiwiHz+eFnv5QTGyYOBMFay+FlkLU=; b=rKNmO3cxYVG/TYHSYuv+aV9DJ+/8Fvi2Q/ClvTi5VdraHF6KT7kk0O+QbhG/X4T7j5 9piu1CTFR+fAeL++LlfD+pPXbtALhns+8BKRlkPbsZy9N1JEWFW6dWGPVS4SiHghZnuX HYTWGUYE3j+bvwqqcDo23MtrVKAQAbcfnNxB8rNK9a2NG0jbti3TXrH+f7tC2SdFtJa9 slTcBp6BOV3s3h8j8bl3gVFp06dU/obo8l6KMNwTB0Ec6OaubrsNwUmi+vUvMX4BuWJe FVCvkGrRepG40KidSZWX5Zr1I7MZNhx2bui4UWWojsl0rxN3Gq/lQtmdXYCGxe+WfqpJ rl4w== X-Gm-Message-State: APjAAAX1Kv3aYrIfLKpfPkgfNfBnKbt0kQXcMu4n/iUTV9rLzPZQ5/6t ln/tuAkec2vlTiIKxwPCIPBfqlqmfvoF9/zpvxDPKQ== X-Received: by 2002:a2e:5d94:: with SMTP id v20mr26415232lje.138.1554989593745; Thu, 11 Apr 2019 06:33:13 -0700 (PDT) MIME-Version: 1.0 References: <1554800820-5412-1-git-send-email-p.paillet@st.com> <1554800820-5412-2-git-send-email-p.paillet@st.com> In-Reply-To: <1554800820-5412-2-git-send-email-p.paillet@st.com> From: Linus Walleij Date: Thu, 11 Apr 2019 15:33:02 +0200 Message-ID: Subject: Re: [PATCH v2 1/3] ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 board To: Pascal PAILLET-LME Cc: "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux@armlinux.org.uk" , "horms+renesas@verge.net.au" , "olof@lixom.net" , "arnd@arndb.de" , "geert+renesas@glider.be" , "biju.das@bp.renesas.com" , Yannick FERTRE , "m.szyprowski@samsung.com" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 9, 2019 at 11:08 AM Pascal PAILLET-LME wrote: > This patch adds stpmic1 support on stm32mp157c ed1 board. > The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 > regulators, 3 power switches, a watchdog and an input for a power on key. > The DMAs are disabled because the PMIC generates a very few traffic and > DMA channels may lack for other usage. > > Signed-off-by: Pascal Paillet Reviewed-by: Linus Walleij Yours, Linus Walleij