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[209.132.180.67]) by mx.google.com with ESMTP id h20si29809776pgn.69.2019.04.11.08.22.48; Thu, 11 Apr 2019 08:23:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="MaYmM/4l"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726936AbfDKPU3 (ORCPT + 99 others); Thu, 11 Apr 2019 11:20:29 -0400 Received: from mail-yw1-f68.google.com ([209.85.161.68]:37416 "EHLO mail-yw1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726640AbfDKPU2 (ORCPT ); Thu, 11 Apr 2019 11:20:28 -0400 Received: by mail-yw1-f68.google.com with SMTP id w66so2196821ywd.4; Thu, 11 Apr 2019 08:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=AXTt1TFBMBOViy/QP1pNCCk2KiS3VbjgXEWNmIrzuNs=; b=MaYmM/4lfJg5wk3kk1Y5WH9pgU+wvFPggreJCBr9j7CpgeJszR8Jf6UbW4RcXVZ+uh nHQL98UeMDcw2n9QRWrF29h86bRwi/EGMXIV73l2lLVWcbHciBNb5pq8HJcP6yWMHyJe qYHDHC/PFSEeV74G/5RBUg32QtTGcfFaVz/PmysqNcdFnGLnF24qlIlRbwL4ClhfVfc+ 9TPIu2IOK1bJwni3WOigblGtinwkz5rGjEollkE4qxeDDAVvRgIJkn98+k7rkdLvQkxr bIM0JO4VZ6GVC1LSf3tvuiR+t6vLWvGv7hL8dOJnqhux8p838KlpUsfHj3HL45Sy5Mh/ GI4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=AXTt1TFBMBOViy/QP1pNCCk2KiS3VbjgXEWNmIrzuNs=; b=S6JBiuJiIKUBS8aAsOVe9ee8Z3Xr5YdoaCCoyLAxRE1wmLh/gf3mlmU+/1W7pls8xp HPEPFtp4UQ5XhEIsS2CSslFyu4CpZSeWLl9pRCiZTimSulBNM54pfoaVMUQR8OpmxyxE N1f65OLgsPtjHVUX5KX7/qbXCNpiYYnD1v3anwHWF7zdbtvsCfDvOntv0l9dLcm3F60E PoMTSGAO6neMUBwDEskAQ0WavDISP9VxxXyMNMaxjzgmSQDx9+MIRLjykAv3vX81eEz1 sKGZgV/tcm2918pExvFMn6J3oOyVOMdt7bXek5rEO+YztoNuKsLF6znHZHw0sUJhsM3J pr+w== X-Gm-Message-State: APjAAAUNcMaub1lBA2YcVntXUSPBdeHV415vlxt/DCnJZsTFwz6u2BME uMYemR4EaZJgfcuXfnsZy0JGNtk6+ak8Mp95pjQ= X-Received: by 2002:a81:6f87:: with SMTP id k129mr40791228ywc.322.1554996027634; Thu, 11 Apr 2019 08:20:27 -0700 (PDT) MIME-Version: 1.0 References: <20190411105720.32357-1-peron.clem@gmail.com> <20190411105720.32357-5-peron.clem@gmail.com> <2957024.jOddxINRMN@jernej-laptop> In-Reply-To: <2957024.jOddxINRMN@jernej-laptop> From: =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= Date: Thu, 11 Apr 2019 17:20:04 +0200 Message-ID: Subject: Re: [PATCH v2 4/8] arm64: dts: allwinner: Add ARM Mali GPU node for H6 To: =?UTF-8?Q?Jernej_=C5=A0krabec?= Cc: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , devicetree , linux-kernel , linux-arm-kernel , dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, 11 Apr 2019 at 17:05, Jernej =C5=A0krabec = wrote: > > Dne =C4=8Detrtek, 11. april 2019 ob 12:57:16 CEST je Cl=C3=A9ment P=C3=A9= ron napisal(a): > > Add the mali gpu node to the H6 device-tree. > > > > Signed-off-by: Cl=C3=A9ment P=C3=A9ron > > --- > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index > > e0dc4a05c1ba..196753110434 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -157,6 +157,20 @@ > > allwinner,sram =3D <&ve_sram 1>; > > }; > > > > + gpu: gpu@1800000 { > > + compatible =3D "allwinner,sun50i-h6-mali", > > + "arm,mali-t720"; > > + reg =3D <0x01800000 0x4000>; > > + interrupts =3D IRQ_TYPE_LEVEL_HIGH>, > > + IRQ_TYPE_LEVEL_HIGH>, > > + IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names =3D "job", "mmu", "gpu"; > > + clocks =3D <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; > > + clock-names =3D "core", "bus"; > > + resets =3D <&ccu RST_BUS_GPU>; > > + status =3D "disabled"; > > Usually self sufficient peripherals are enabled by default in DTSI. I follow the other Mali Midgard (rk3399, rk3288) syntax. But I think you're right here, will go for an update I think. Clement > > > + }; > > + > > syscon: syscon@3000000 { > > compatible =3D "allwinner,sun50i-h6-system- > control", > > "allwinner,sun50i-a64- > system-control"; > > > >