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[2003:f1:33c8:ad00:10b8:127c:436:7d1]) by smtp.googlemail.com with ESMTPSA id h84sm16745965wmf.15.2019.04.13.10.15.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 13 Apr 2019 10:15:47 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mjourdan@baylibre.com, Martin Blumenstingl Subject: [PATCH 2/3] ARM: dts: meson8m2: update the offset of the canvas module Date: Sat, 13 Apr 2019 19:15:31 +0200 Message-Id: <20190413171532.25967-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413171532.25967-1-martin.blumenstingl@googlemail.com> References: <20190413171532.25967-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With the Meson8m2 SoC the canvas module was moved from offset 0x20 (Meson8) to offset 0x48 (same as on Meson8b). The offsets inside the canvas module are identical. Correct the offset so the driver uses the correct registers. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8m2.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index bb87b251e16d..e88c36d47e5c 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -14,6 +14,16 @@ compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; }; +&dmcbus { + /* the offset of the canvas registers has changed compared to Meson8 */ + /delete-node/ video-lut@20; + + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x48 0x14>; + }; +}; + ðmac { compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000 -- 2.21.0