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[209.132.180.67]) by mx.google.com with ESMTP id k185si48421182pgc.450.2019.04.16.00.39.26; Tue, 16 Apr 2019 00:39:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728548AbfDPHif (ORCPT + 99 others); Tue, 16 Apr 2019 03:38:35 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:43946 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726783AbfDPHie (ORCPT ); Tue, 16 Apr 2019 03:38:34 -0400 X-UUID: 4de3dd16e34543d492c325b53fead0df-20190416 X-UUID: 4de3dd16e34543d492c325b53fead0df-20190416 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 580156060; Tue, 16 Apr 2019 15:38:26 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 15:38:24 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 15:38:17 +0800 Message-ID: <1555400297.29874.2.camel@mtksdaap41> Subject: Re: [PATCH v2 17/25] drm/mediatek: add background color input select function for ovl/ovl_2l From: CK Hu To: CC: , , , , , , , , , , , Date: Tue, 16 Apr 2019 15:38:17 +0800 In-Reply-To: <1553667561-25447-18-git-send-email-yongqiang.niu@mediatek.com> References: <1553667561-25447-1-git-send-email-yongqiang.niu@mediatek.com> <1553667561-25447-18-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 4C5F8F34B57783A584B4DE76991E398F3A27349D402B9A1526F939A8676668EF2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Wed, 2019-03-27 at 14:19 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add background color input select function for ovl/ovl_2l > > ovl include 4 DRAM layer and 1 background color layer > ovl_2l include 4 DRAM layer and 1 background color layer > DRAM layer frame buffer data from render hardware, GPU for example. > backgournd color layer is embed in ovl/ovl_2l, we can only set > it color, but not support DRAM frame buffer. > > for ovl0->ovl0_2l direct link usecase, > we need set ovl0_2l background color intput select from ovl0 > if render send DRAM buffer layer number <=4, all these layer read > by ovl. > layer0 is at the bottom of all layers. > layer3 is at the top of all layers. > if render send DRAM buffer layer numbfer >=4 && <=6 > ovl0 read layer0~3 > ovl0_2l read layer4~5 > layer5 is at the top ot all these layers. > > the decision of how to setting ovl0/ovl0_2l read these layer data > is controlled in mtk crtc, which will be another patch > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index a0ab760..c226284 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -27,6 +27,8 @@ > #define DISP_REG_OVL_EN 0x000c > #define DISP_REG_OVL_RST 0x0014 > #define DISP_REG_OVL_ROI_SIZE 0x0020 > +#define DISP_REG_OVL_DATAPATH_CON 0x0024 > +#define OVL_BGCLR_SEL_IN BIT(2) > #define DISP_REG_OVL_ROI_BGCLR 0x0028 > #define DISP_REG_OVL_SRC_CON 0x002c > #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) > @@ -245,6 +247,26 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, > mtk_ovl_layer_on(comp, idx); > } > > +static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp, > + enum mtk_ddp_comp_id prev) > +{ > + int is_ovl = 0; > + > + if (prev == DDP_COMPONENT_OVL0 || > + prev == DDP_COMPONENT_OVL0_2L || > + prev == DDP_COMPONENT_OVL1_2L) > + is_ovl = 1; I think this logic should be moved to mtk crtc and OVL need not to care about which component is in front of it. Regards, CK > + > + mtk_ddp_write_mask((is_ovl << 2), comp, > + DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN); > +} > + > +static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) > +{ > + mtk_ddp_write_mask(0, comp, > + DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN); > +} > + > static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { > .config = mtk_ovl_config, > .start = mtk_ovl_start, > @@ -255,6 +277,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, > .layer_on = mtk_ovl_layer_on, > .layer_off = mtk_ovl_layer_off, > .layer_config = mtk_ovl_layer_config, > + .bgclr_in_on = mtk_ovl_bgclr_in_on, > + .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > static int mtk_disp_ovl_bind(struct device *dev, struct device *master,