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[209.132.180.67]) by mx.google.com with ESMTP id h6si44900781pgv.302.2019.04.16.01.12.55; Tue, 16 Apr 2019 01:13:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728637AbfDPIMW (ORCPT + 99 others); Tue, 16 Apr 2019 04:12:22 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:36772 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725840AbfDPIMW (ORCPT ); Tue, 16 Apr 2019 04:12:22 -0400 X-UUID: 87c546c982b341adb8fc2bf989b38a1e-20190416 X-UUID: 87c546c982b341adb8fc2bf989b38a1e-20190416 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 816406446; Tue, 16 Apr 2019 16:12:16 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 16:12:14 +0800 Received: from mtkslt303.mediatek.inc (10.21.14.116) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 16:12:14 +0800 From: Erin Lo To: Matthias Brugger , Rob Herring , Mark Rutland CC: , srv_heupstream , , , , , , , Subject: [PATCH v10] Add basic and clock support for Mediatek MT8183 SoC Date: Tue, 16 Apr 2019 16:12:10 +0800 Message-ID: <1555402331-5343-1-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 35F24435D2C66066E16C2512E8FB759B83A095EA45967CA7916527E2AC6E26E42000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8183 is a SoC based on 64bit ARMv8 architecture. It contains 4 CA53 and 4 CA73 cores. MT8183 share many HW IP with MT65xx series. This patchset was tested on MT8183 evaluation board and use correct clock to shell. Based on v5.1-rc1 and http://lists.infradead.org/pipermail/linux-mediatek/2019-March/017963.html Change in v10: Add the L2 cache node to prevent warning on unable to detect cache hierarchy. Change in v9: Remove pio node since binding is not documented yet Change in v8: 1. Fix interrupt-parent of pio node 2. Remove pinfunc.h and spi node patches Change in v7: 1. Place all the MMIO peripherals under one or more simple-bus nodes 2. Make the pinfunc.h and spi node into seperate patch 3. Modify SPIs pamerater from 4 back to 3 and remove patch "support 4 interrupt parameters for sysirq" 4. Rename intpol-controller to interrupt-controller 5. Rename pinctrl@1000b000 to pinctrl@10005000 Change in v6: 1. Remove power and iommu nodes 2. Fix dtb build warning 3. Fix pinctrl binding doc 4. Fix '_' in node names Change in v5: 1. Collect all device tree nodes to the last patch 2. Add PMU 3. Add Signed-off-by 4. Remove clock driver code and binding doc 5. Add pinctrl, iommu, spi, and pwrap nodes Change in v4: 1. Correct syntax error in dtsi 2. Add MT8183 clock support Change in v3: 1. Fill out GICC, GICH, GICV regions 2. Update Copyright to 2018 Change in v2: 1. Split dt-bindings into different patches 2. Correct bindings for supported SoCs (mtk-uart.txt) Ben Ho (1): arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 329 ++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi -- 1.9.1