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From:   Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To:     Vidya Sagar <vidyas@nvidia.com>,
        "jingoohan1@gmail.com" <jingoohan1@gmail.com>,
        "gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "Jisheng.Zhang@synaptics.com" <Jisheng.Zhang@synaptics.com>,
        "thierry.reding@gmail.com" <thierry.reding@gmail.com>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "kthota@nvidia.com" <kthota@nvidia.com>,
        "mmaddireddy@nvidia.com" <mmaddireddy@nvidia.com>,
        "sagar.tv@gmail.com" <sagar.tv@gmail.com>
Subject: RE: [PATCH 2/2] PCI: dwc: Export APIs to support .remove()
 implementation
Thread-Topic: [PATCH 2/2] PCI: dwc: Export APIs to support .remove()
 implementation
Thread-Index: AQHU6uDUR7xXwQdAhE+dc4S79C4wm6Y+3dOQ
Date:   Tue, 16 Apr 2019 13:43:06 +0000
Message-ID: <305100E33629484CBB767107E4246BBB0A22B66D@de02wembxa.internal.synopsys.com>
References: <1554380425-29215-1-git-send-email-vidyas@nvidia.com>
 <1554380425-29215-3-git-send-email-vidyas@nvidia.com>
In-Reply-To: <1554380425-29215-3-git-send-email-vidyas@nvidia.com>
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On Thu, Apr 4, 2019 at 13:20:24, Vidya Sagar <vidyas@nvidia.com> wrote:

> Export all configuration space access APIs and also other APIs to
> support host controller drivers of Designware core based

s/Designware/DesignWare

> implementations while adding support for .remove() hook to build their
> respective drivers as modules
>=20
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c |  4 +++
>  drivers/pci/controller/dwc/pcie-designware.c      | 38 +++++++++++++++++=
++++++
>  drivers/pci/controller/dwc/pcie-designware.h      | 35 ++++-------------=
----
>  3 files changed, 48 insertions(+), 29 deletions(-)
>=20
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/=
pci/controller/dwc/pcie-designware-host.c
> index d7881490282d..2a5332e5ccfa 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -333,6 +333,7 @@ void dw_pcie_msi_init(struct pcie_port *pp)
>  	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
>  			    upper_32_bits(msi_target));
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
> =20
>  int dw_pcie_host_init(struct pcie_port *pp)
>  {
> @@ -515,6 +516,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  		dw_pcie_free_msi(pp);
>  	return ret;
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_host_init);
> =20
>  void dw_pcie_host_deinit(struct pcie_port *pp)
>  {
> @@ -522,6 +524,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
>  	pci_remove_root_bus(pp->root_bus);
>  	dw_pcie_free_msi(pp);
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
> =20
>  static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bu=
s *bus,
>  				     u32 devfn, int where, int size, u32 *val,
> @@ -731,3 +734,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	val |=3D PORT_LOGIC_SPEED_CHANGE;
>  	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/c=
ontroller/dwc/pcie-designware.c
> index 31f6331ca46f..f98e2f284ae1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -40,6 +40,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val=
)
> =20
>  	return PCIBIOS_SUCCESSFUL;
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_read);
> =20
>  int dw_pcie_write(void __iomem *addr, int size, u32 val)
>  {
> @@ -57,6 +58,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val=
)
> =20
>  	return PCIBIOS_SUCCESSFUL;
>  }
> +EXPORT_SYMBOL_GPL(dw_pcie_write);
> =20
>  u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
>  		       size_t size)
> @@ -89,6 +91,42 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __i=
omem *base, u32 reg,
>  		dev_err(pci->dev, "Write DBI address failed\n");
>  }
> =20
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> +{
> +	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writel_dbi);
> +
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> +{
> +	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readl_dbi);
> +
> +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
> +{
> +	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writew_dbi);
> +
> +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
> +{
> +	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readw_dbi);
> +
> +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
> +{
> +	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writeb_dbi);
> +
> +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
> +{
> +	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readb_dbi);
> +
>  static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 r=
eg)
>  {
>  	u32 offset =3D PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/c=
ontroller/dwc/pcie-designware.h
> index ea8d1caf11c5..86df36701a37 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -265,35 +265,12 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int i=
ndex,
>  			 enum dw_pcie_region_type type);
>  void dw_pcie_setup(struct dw_pcie *pci);
> =20
> -static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 =
val)
> -{
> -	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
> -}
> -
> -static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> -{
> -	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
> -}
> -
> -static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 =
val)
> -{
> -	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
> -}
> -
> -static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
> -{
> -	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
> -}
> -
> -static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 v=
al)
> -{
> -	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
> -}
> -
> -static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
> -{
> -	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
> -}
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val);
> +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val);
> +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg);
> =20
>  static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32=
 val)
>  {
> --=20
> 2.7.4

Seems harmless. After word replacement, ack for the whole patch:

Acked-by: Gustavo Pimentel=20
<gustavo.pimentel@synopsys.com>

Thanks
Gustavo=20
Pimentel