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[209.132.180.67]) by mx.google.com with ESMTP id b8si41212397pfd.55.2019.04.16.12.30.26; Tue, 16 Apr 2019 12:30:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=K8caSlxJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730441AbfDPT2T (ORCPT + 99 others); Tue, 16 Apr 2019 15:28:19 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2723 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727180AbfDPT2T (ORCPT ); Tue, 16 Apr 2019 15:28:19 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Apr 2019 12:28:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 12:28:17 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 16 Apr 2019 12:28:17 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 19:28:17 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 19:28:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 19:28:16 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 16 Apr 2019 12:28:16 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V3 05/16] PCI: dwc: Move config space capability search API Date: Wed, 17 Apr 2019 00:57:19 +0530 Message-ID: <20190416192730.15681-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190416192730.15681-1-vidyas@nvidia.com> References: <20190416192730.15681-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555442894; bh=Et7+y3SGYsf9Klq9C/6q+Ekm1G6og5wQm0Eo5Ui1ka0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=K8caSlxJCKmhiBuwtkY/t4wFxD0VGwb3RVn1lLiAB7Nl3YfDhMRgEEAnArCjeYtwK IxhTbXmhpJy9tamtGReH6lfSztjTLIXEzaoBT/TATl1F+4jwayxGMSz4SCDNwkDNMv jmUUchSfx+ltgWj9+oMwg2FwVWEt+eCdn1aN0xbjdbiNy94O1iiLm4TMTz/iNKFCXR MiFN2crmqBfbJjzvNSnCVO8hAHxPWDjJD5Z4z08AHZTqkifmB0BgClbtA6/62Z3ziK W+Uref02AxDcMF7CYz9YKBVc8ERb1ky50vsxpFKRDcaJukJ5utg7jLpVkmnOCxPYIo ylutqAECAHpOg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org move PCIe config space capability search API to common designware file as this can be used by both host and ep mode codes. Signed-off-by: Vidya Sagar --- Changes from [v2]: * None Changes from [v1]: * Removed dw_pcie_find_next_ext_capability() API from here and made a separate patch for that .../pci/controller/dwc/pcie-designware-ep.c | 37 +------------------ drivers/pci/controller/dwc/pcie-designware.c | 33 +++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 + 3 files changed, 37 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 24f5a775ad34..b9d9c9a4ba6d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) __dw_pcie_ep_reset_bar(pci, bar, 0); } -static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) -{ - u8 cap_id, next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; - cap_id = (reg & 0x00ff); - - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) - return 0; - - if (cap_id == cap) - return cap_ptr; - - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); -} - -static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) -{ - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - if (!next_cap_ptr) - return 0; - - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); -} - static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, struct pci_epf_header *hdr) { @@ -591,9 +558,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); return -ENOMEM; } - ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); dw_pcie_setup(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index f98e2f284ae1..d68c123e409c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -20,6 +20,39 @@ #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) +static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, + u8 cap) +{ + u8 cap_id, next_cap_ptr; + u16 reg; + + reg = dw_pcie_readw_dbi(pci, cap_ptr); + next_cap_ptr = (reg & 0xff00) >> 8; + cap_id = (reg & 0x00ff); + + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) +{ + u8 next_cap_ptr; + u16 reg; + + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); + next_cap_ptr = (reg & 0x00ff); + + if (!next_cap_ptr) + return 0; + + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 86df36701a37..4ccd4c706ddb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -247,6 +247,8 @@ struct dw_pcie { #define to_dw_pcie_from_ep(endpoint) \ container_of((endpoint), struct dw_pcie, ep) +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); + int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -- 2.17.1