Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp3493481yba; Tue, 16 Apr 2019 12:30:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqyReovr2Wm0Fv+rWDG1NxhN+CBZAfLVOtGxq91+LIw/ly7rPYdyCdwLBtpfPKTdUhetjz4s X-Received: by 2002:a62:2a97:: with SMTP id q145mr84608181pfq.22.1555443050510; Tue, 16 Apr 2019 12:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555443050; cv=none; d=google.com; s=arc-20160816; b=w9PnZB1CoaRB50Afvzvl9OBoCXkJTF0YpYKFJCmtSou96ZsROTLl663UeiS7Vh7yCK 0dZ0clf52SRhyqWSdVAKbMMReO5TaqZKnubdGD8Z9kSkyQIKcqzIHaOibh1dckrdD2lU kOXpvi6fNPal70LdUVGL6YH59Coj1wDk/tXRyW9cJGYpsn6Cqc1EW1ASV+Apkf/3iSrX ClWcEt+U+mbLX4LuTexsfxhuc8vS2KX9COQWCVSqwyuoD6RQc01ADNQRaLmfJmXY0nUD 3uuqu264nmzWZ2ZA3EAz9lZgpJpgP4neFK6onE7GPLBplb42kWQzraj3VzCB3QDEc9tW Uq8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=XEZPGmVmqcpr9xs3N7W0Xgd9hI4J9W4Ea5nBCX73V6U=; b=S8GsUxFIs20Hwdht7bGdGZSVp10kMkIx78NDQamEbhwlvnekbsahn5tnEmok0G+0QV /pg+mwNh4a0OSjAppe7RWsWd0l1r1vNjmPz5kRQePo4WZVaF5G1u64WmciNDH7JuDMP9 4uCxnH2J2Xh82vNk8jHqE9T6wFesOSckjSFSfONjAjKdBAHYFEUVrcolTO/WggAbGxaF YbknqerKxtiynRs6dFhnALJbhDTJPodRA+BXWPGhbYzMBFX+vQg7KltctNnfNsHrRfDL IneTI2kWbdXabcVDBzEq6F5AlkuLkatjqRWVvwZHDd/7ltU5mM2CgVp1gWJejUIuhhWr cIlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="H/5PBFM5"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h69si22041996pfc.100.2019.04.16.12.30.34; Tue, 16 Apr 2019 12:30:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="H/5PBFM5"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730476AbfDPT20 (ORCPT + 99 others); Tue, 16 Apr 2019 15:28:26 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6708 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727180AbfDPT2Z (ORCPT ); Tue, 16 Apr 2019 15:28:25 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Apr 2019 12:28:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 12:28:25 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 16 Apr 2019 12:28:25 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 19:28:24 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 19:28:24 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 19:28:24 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 16 Apr 2019 12:28:24 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V3 06/16] PCI: dwc: Add ext config space capability search API Date: Wed, 17 Apr 2019 00:57:20 +0530 Message-ID: <20190416192730.15681-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190416192730.15681-1-vidyas@nvidia.com> References: <20190416192730.15681-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555442885; bh=XEZPGmVmqcpr9xs3N7W0Xgd9hI4J9W4Ea5nBCX73V6U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=H/5PBFM5qIVrsw3/1dPDOGufNjXJLdceMPf9Bl8u9gQ1LweqHVbU3+SGm/eCMtVaq EtZRO9dvPqFZ0FjtlFPfWVzWqkdY++rFyZAZR0ZwnA0sVvlK07RbTaez561lYO01T5 0WEfruPjDrftVOPk1e5r4PgBNZi/ijL6IooelzT475lSjYHPL+AbQPhRaxTLpRtYeP dqPiLna/HPXW6u0Qv29m00Y0C4tIVsYMyGVZpaSg4lvBf7OHFszpLbZPl/R9pwPjso IoGwOlrcYjDX6orq47yAEILB2O7dNMR332cs3KfrRQfV6IKaLg2CSlXD9yB9mKMPU6 0WpBqxjTlY01g== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add extended configuration space capability search API using struct dw_pcie * pointer Signed-off-by: Vidya Sagar --- Changes from [v2]: * None Changes from [v1]: * This is a new patch in v2 series drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d68c123e409c..44c0ba078452 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); } +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start, + int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + header = dw_pcie_readl_dbi(pci, pos); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = dw_pcie_readl_dbi(pci, pos); + } + + return 0; +} + +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap) +{ + return dw_pcie_find_next_ext_capability(pci, 0, cap); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 4ccd4c706ddb..fa41d675c48f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -248,6 +248,7 @@ struct dw_pcie { container_of((endpoint), struct dw_pcie, ep) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -- 2.17.1