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[209.132.180.67]) by mx.google.com with ESMTP id k9si51035782pgc.156.2019.04.17.01.51.05; Wed, 17 Apr 2019 01:51:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@alien8.de header.s=dkim header.b=ahGUkq0m; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=alien8.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728815AbfDQIuP (ORCPT + 99 others); Wed, 17 Apr 2019 04:50:15 -0400 Received: from mail.skyhub.de ([5.9.137.197]:57750 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726237AbfDQIuP (ORCPT ); Wed, 17 Apr 2019 04:50:15 -0400 Received: from zn.tnic (p200300EC2F112E000C2D4197130645E8.dip0.t-ipconnect.de [IPv6:2003:ec:2f11:2e00:c2d:4197:1306:45e8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 9F84C1EC04CD; Wed, 17 Apr 2019 10:50:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1555491013; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:references; bh=Agt5mFRMnVWGgmmfPL7gPuUc6pRfbTwS8vO0+jLpWZM=; b=ahGUkq0mLkRAnyiYuMCMEO17Jkyv8ywx0KvcbsKwyFUNj8ci+I03MNIUh8X6813aHRQqC/ BMEOuZ+wuf2Tpebw/xxcT0DQYd7TzwfFUYasoGZLFeur7QrH1px/bIzUXcBeLKX3E35WKE S/ZjZCXaIn/LluFPAQBtunPMq1BqGgA= Date: Wed, 17 Apr 2019 10:50:08 +0200 From: Borislav Petkov To: Linus Torvalds Cc: Michael Matz , x86-ml , lkml Subject: [PATCH] asm/io: Correct output operand specification of the MMIO write* routines Message-ID: <20190417085008.GB20492@zn.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, I'm looking at c1f64a58003f ("x86: MMIO and gcc re-ordering issue") and trying to figure out was there any particular reason the address to the MMIO write routines had to be an input operand? Because if not, please have a look at the patch below. It boots here and from the couple of resulting asm I looked at, it doesn't change. But there might be some other aspect I'm missing so... Thx. --- From: Borislav Petkov Currently, all the MMIO write operations specify the output @addr operand as an input operand to the extended asm statement. This works because the asm statement is marked volatile and "memory" is on the clobbered list, preventing gcc from optimizing around an inline asm without output operands. However, the more correct way of writing this is to make the target MMIO write address an input *and* output operand so that gcc is aware that modifications have happened through it. Now, one could speculate further and say, the memory clobber could be dropped: *P; // (1) mmio_write("..." : "+m" (whatever)); // no memory clobber *P; // (2) but then gcc would at -O2 optimize the access in (2) by replacing it with its value from (1), which would be wrong. The solution would be sticking a memory barrier after (1) but then that puts the onus on the programmer to make sure it doesn't get forgotten, and that is the wrong approach: generic interfaces like that should JustWork(tm) so let's leave the "memory" clobber. Signed-off-by: Borislav Petkov Cc: Michael Matz --- arch/x86/include/asm/io.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 686247db3106..33c4d8776b47 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -49,10 +49,11 @@ static inline type name(const volatile void __iomem *addr) \ { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ :"m" (*(volatile type __force *)addr) barrier); return ret; } -#define build_mmio_write(name, size, type, reg, barrier) \ -static inline void name(type val, volatile void __iomem *addr) \ -{ asm volatile("mov" size " %0,%1": :reg (val), \ -"m" (*(volatile type __force *)addr) barrier); } +#define build_mmio_write(name, size, type, reg, barrier) \ +static inline void name(type val, volatile void __iomem *mem) \ +{ asm volatile("mov" size " %1,%0" \ + : "+m" (*(volatile type __force *)mem) \ + : reg (val) barrier); } build_mmio_read(readb, "b", unsigned char, "=q", :"memory") build_mmio_read(readw, "w", unsigned short, "=r", :"memory") -- 2.21.0 -- Regards/Gruss, Boris. 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