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[209.132.180.67]) by mx.google.com with ESMTP id h9si45121091pgn.145.2019.04.17.02.42.16; Wed, 17 Apr 2019 02:42:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731604AbfDQJko (ORCPT + 99 others); Wed, 17 Apr 2019 05:40:44 -0400 Received: from mx2.suse.de ([195.135.220.15]:53118 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726237AbfDQJko (ORCPT ); Wed, 17 Apr 2019 05:40:44 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 251ABAF9C; Wed, 17 Apr 2019 09:40:43 +0000 (UTC) Date: Wed, 17 Apr 2019 11:40:42 +0200 Message-ID: From: Takashi Iwai To: Timo Wischer Cc: , , , , Subject: Re: [ALSA patch] [PATCH] ALSA: pcm: Enable MMAP status and control for ARMv7 and ARMv8 In-Reply-To: <5946b2b4-ecf7-8266-2998-a19b7d9a2d2c@de.adit-jv.com> References: <1555490771-13242-1-git-send-email-twischer@de.adit-jv.com> <5946b2b4-ecf7-8266-2998-a19b7d9a2d2c@de.adit-jv.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/25.3 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 17 Apr 2019 11:30:10 +0200, Timo Wischer wrote: > > On 4/17/19 11:21, Takashi Iwai wrote: > > On Wed, 17 Apr 2019 10:46:11 +0200, > > wrote: > >> From: Timo Wischer > >> > >> Since ARMv7 hardware cache coherence is supported. > >> "The SCU maintains coherency between the individual data caches in the > >> Cortex-A5 MPCore processor using a variation of the MOESI protocol" [1]. > >> > >> Therefore this patch enables the MMAP access to the status and control > >> structures. This avoids HWSYYNC ioctl calls and therefore lowers the CPU > >> usage. > >> > >> [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0434c/ > >> BABJECBF.html > > Interesting... I thought it would never work properly on ARM. > > If it really works like that, I'd happily apply the change. > > But I'd like to hear a confirmation from ARM people before merging > > such an intensive change. > > Hi Takashi, > > do I need to send this patch to any other mailing list or do you think > some corresponding guy is already on the lists I have used? Well, maybe we need to ping ARM people if no one on the lists you Cc'ed give comments. Let's see. Takashi > > > > > > > thanks, > > > > Takashi > > > >> Signed-off-by: Timo Wischer > >> --- > >> sound/core/pcm_native.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c > >> index 1d84529..b8019ef 100644 > >> --- a/sound/core/pcm_native.c > >> +++ b/sound/core/pcm_native.c > >> @@ -3225,7 +3225,8 @@ static __poll_t snd_pcm_poll(struct file *file, poll_table *wait) > >> * Only on coherent architectures, we can mmap the status and the control records > >> * for effcient data transfer. On others, we have to use HWSYNC ioctl... > >> */ > >> -#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) > >> +#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) || \ > >> + (defined(CONFIG_ARM) && defined(CONFIG_CPU_V7)) || defined(CONFIG_ARM64) > >> /* > >> * mmap status record > >> */ > >> -- > >> 2.7.4 > >> > >> _______________________________________________ > >> Patch mailing list > >> Patch@alsa-project.org > >> https://mailman.alsa-project.org/mailman/listinfo/patch > >> >