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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Lucas Stach <l.stach@pengutronix.de>,
        Abel Vesa <abel.vesa@nxp.com>, Peng Fan <peng.fan@nxp.com>
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        <linux-arm-kernel@lists.infradead.org>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>
Subject: Re: [RESEND v2] soc: imx: Add generic i.MX8 SoC driver
Thread-Topic: [RESEND v2] soc: imx: Add generic i.MX8 SoC driver
Thread-Index: AQHU4M8x51owZIDO7UOOFQ/teNRhvw==
Date:   Thu, 18 Apr 2019 22:01:24 +0000
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On 3/28/2019 6:43 PM, Leonard Crestez wrote:=0A=
> On Fri, 2019-03-22 at 16:49 +0000, Abel Vesa wrote:=0A=
>> Add generic i.MX8 SoC driver along with the i.MX8MQ SoC specific code.=
=0A=
>> For now, only i.MX8MQ revision B1 is supported. For any other, i.MX8MQ=
=0A=
>> revision it will print 'unknown'.=0A=
> =0A=
>> +#define REV_B1				0x21=0A=
>> +=0A=
>> +#define IMX8MQ_SW_INFO_B1		0x40=0A=
>> +#define IMX8MQ_SW_MAGIC_B1		0xff0055aa=0A=
>> +=0A=
>> +	np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");+=0A=
>> +	ocotp_base =3D of_iomap(np, 0);=0A=
>> +=0A=
>> +	magic =3D readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);=0A=
>> +	if (magic =3D=3D IMX8MQ_SW_MAGIC_B1)=0A=
>> +		rev =3D REV_B1;=0A=
> =0A=
> This is based on ATF code in vendor tree, but shouldn't we have some=0A=
> sort of explanation for this "magic"?=0A=
> =0A=
> Looking at the OCOTP driver reg 0x40 is IMX_OCOTP_ADDR_DATA2 and it's=0A=
> used as part of fuse writes. According to the driver code 8mq is=0A=
> compatible with 7d and this write path is enabled for imx8mq-ocotp.=0A=
=0A=
After further digging in NXP manuals and uboot sources it seems that =0A=
imx8mq ocotp is like imx6 rather than imx7. Posted fix for nvmem driver:=0A=
=0A=
https://patchwork.kernel.org/patch/10908081/=0A=
=0A=
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>=0A=
=0A=
It might still be nice to find a way to identify imx8mq B0.=0A=