Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp317182yba; Sat, 20 Apr 2019 03:15:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqx078pK5APankqQhGUK+xSCHNVOHJjjdUJKdKlVyo6Nyn++R09JUmAN5/O2DbBZ+iSPCs+P X-Received: by 2002:a17:902:8349:: with SMTP id z9mr8719710pln.144.1555755354279; Sat, 20 Apr 2019 03:15:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555755354; cv=none; d=google.com; s=arc-20160816; b=Tl+NKCUvnyEc9uP+OcGfXPEgzyUoPRswOMN+6KK5hyyfTVO8OrT72T+0Ep6GXYdnzw DzAVerKA8mQgwbxIFuJhDIrDFWUrFotCK1J+KGgHrfMUUa0ESo8MxDERYPnYTvO++KWq e99GikOkpCRxAryC2inlP0TOGJznEpbeg9GHfgmym7e+khfRjq8MwjdVWrXx/gVea+/a 1N8TYn2+fymPI7WHxBmsncowefKQBiWTGlbmgM8hJByxdpSCaWTDqLULJqi2MrkcIIjl TFnOcMhTKaRLK5pOedRf+Hn3Iwbu6WkuS09EP7SuaLPSR/tsT23jFrsUhqU5tptg40ee d18g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fwMtKmHI0LHaI4B1vd4OY0LZJNxjgh5qJQeE541Muvs=; b=qsX46ffxlPhVS99et2iAJI0vLhzrjJv24HiXkNs0gYdEDZPBC2/ZiIMkzjOkl9OvUy ey0Q/iEy/TP1n/1QeYZcp6Uz3YgSTc7jjJWSYX+mo+27zdcJfybhsQZnyvav0Jezu8wS dWmOTKC8ShgkgwZfYVygo0Lu4TOR4P9vPyChEQRmlDDqmQ20sslQ5E5MnrKwATzN2HZA HEc30tFxKLGgm6NzAAAcfL467205G90PRS3CFuTdznYKBc5kVFx5i9x1W9Gs4opCJ9P1 fwvEeeW4HP/IZU7ceb6qOpZKY4Nwz7YWh3uSamT7zS+f718E1aPLG5XB8eEW02kyCfw6 kapw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dpkeC95P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l8si7372334plt.347.2019.04.20.03.15.39; Sat, 20 Apr 2019 03:15:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dpkeC95P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728282AbfDTKLv (ORCPT + 99 others); Sat, 20 Apr 2019 06:11:51 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59444 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728243AbfDTKLr (ORCPT ); Sat, 20 Apr 2019 06:11:47 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x3KABL8e081031; Sat, 20 Apr 2019 05:11:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1555755081; bh=fwMtKmHI0LHaI4B1vd4OY0LZJNxjgh5qJQeE541Muvs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dpkeC95P7Hw6dJpY+q/b1ONrGi4GZ0dyciymRt5gazeATIkGoS1mF6mfgsh+4WcYb TnIuY7IO1HIbeelBuXiCALkiBb3lDLNAT4r7PNeUcVpy7pnNL82qnbGug37QZWexNW 9sJ2F/5+fSu6WVmxBtdnCYCVHUb262vh6U02ntas= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x3KABLnL098500 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 20 Apr 2019 05:11:21 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Sat, 20 Apr 2019 05:11:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Sat, 20 Apr 2019 05:11:21 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x3KAAHa4070234; Sat, 20 Apr 2019 05:11:17 -0500 From: Lokesh Vutla To: Marc Zyngier , Santosh Shilimkar , Rob Herring , Nishanth Menon , , CC: Linux ARM Mailing List , , Tero Kristo , Sekhar Nori , Tony Lindgren , , Peter Ujfalusi , Grygorii Strashko , Lokesh Vutla , Device Tree Mailing List Subject: [PATCH v7 13/14] irqchip: ti-sci-inta: Add msi domain support Date: Sat, 20 Apr 2019 15:39:49 +0530 Message-ID: <20190420100950.7997-14-lokeshvutla@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190420100950.7997-1-lokeshvutla@ti.com> References: <20190420100950.7997-1-lokeshvutla@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a msi domain that is child to the INTA domain. Clients uses the INTA msi bus layer to allocate irqs in this msi domain. Signed-off-by: Lokesh Vutla --- Changes since v6: - Updated to get device id from platform device. drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-ti-sci-inta.c | 40 ++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7c84a71bcd88..1fab40487d63 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -441,6 +441,7 @@ config TI_SCI_INTA_IRQCHIP depends on TI_SCI_PROTOCOL select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY + select TI_SCI_INTA_MSI_DOMAIN help This enables the irqchip driver support for K3 Interrupt aggregator over TI System Control Interface available on some new TI's SoCs. diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c index 71e5b45ab4ce..53a356795ebf 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,9 @@ #define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \ (TI_SCI_DEV_ID_MASK)) #define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK)) +#define TO_HWIRQ(dev, index) ((((dev) & TI_SCI_DEV_ID_MASK) << \ + TI_SCI_DEV_ID_SHIFT) | \ + ((index) & TI_SCI_IRQ_ID_MASK)) #define MAX_EVENTS_PER_VINT 64 #define VINT_ENABLE_SET_OFFSET 0x0 @@ -496,9 +500,34 @@ static const struct irq_domain_ops ti_sci_inta_irq_domain_ops = { .alloc = ti_sci_inta_irq_domain_alloc, }; +static struct irq_chip ti_sci_inta_msi_irq_chip = { + .name = "MSI-INTA", + .flags = IRQCHIP_SUPPORTS_LEVEL_MSI, +}; + +static void ti_sci_inta_msi_set_desc(msi_alloc_info_t *arg, + struct msi_desc *desc) +{ + struct platform_device *pdev = to_platform_device(desc->dev); + + arg->desc = desc; + arg->hwirq = TO_HWIRQ(pdev->id, desc->inta.dev_index); +} + +static struct msi_domain_ops ti_sci_inta_msi_ops = { + .set_desc = ti_sci_inta_msi_set_desc, +}; + +static struct msi_domain_info ti_sci_inta_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_LEVEL_CAPABLE), + .ops = &ti_sci_inta_msi_ops, + .chip = &ti_sci_inta_msi_irq_chip, +}; + static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) { - struct irq_domain *parent_domain, *domain; + struct irq_domain *parent_domain, *domain, *msi_domain; struct device_node *parent_node, *node; struct ti_sci_inta_irq_domain *inta; struct device *dev = &pdev->dev; @@ -563,6 +592,15 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) return -ENOMEM; } + msi_domain = ti_sci_inta_msi_create_irq_domain(of_node_to_fwnode(node), + &ti_sci_inta_msi_domain_info, + domain); + if (!msi_domain) { + irq_domain_remove(domain); + dev_err(dev, "Failed to allocate msi domain\n"); + return -ENOMEM; + } + INIT_LIST_HEAD(&inta->vint_list); mutex_init(&inta->vint_mutex); -- 2.21.0