Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S263141AbUDLW3j (ORCPT ); Mon, 12 Apr 2004 18:29:39 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S263142AbUDLW3j (ORCPT ); Mon, 12 Apr 2004 18:29:39 -0400 Received: from hqemgate00.nvidia.com ([216.228.112.144]:34573 "EHLO hqemgate00.nvidia.com") by vger.kernel.org with ESMTP id S263141AbUDLW3b (ORCPT ); Mon, 12 Apr 2004 18:29:31 -0400 Date: Mon, 12 Apr 2004 17:29:28 -0500 From: Terence Ripperda To: Linux Kernel Mailing List Cc: tripperda@nvidia.com Subject: PAT support Message-ID: <20040412222928.GP506@hygelac> Reply-To: Terence Ripperda Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="i0/AhcQY5QxfSsSZ" Content-Disposition: inline User-Agent: Mutt/1.4i X-Accept-Language: en X-Operating-System: Linux hrothgar 2.6.4 X-OriginalArrivalTime: 12 Apr 2004 22:29:29.0934 (UTC) FILETIME=[9EEBEEE0:01C420DD] Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 15792 Lines: 214 --i0/AhcQY5QxfSsSZ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi all, quite a while back, I sent out email about adding Page Attribute Table support to the kernel (http://www.ker neltraffic.org/kernel-traffic/kt20030616_219.html#3). At the time, the concern was being able to mark remapped i/o pages Write Combined in the case that we ran out of MTRRs to do so. This was mainly for the agp aperture and framebuffer. With PCI Express systems coming out, the need changes slightly. PCI Express does not have a centralized aperture like agp that can be marked WC. Instead, individual system pages of memory need to be marked WC via PAT in the page tables. This significantly increases the need for PAT support under linux to maintain high performance levels on PCI Express systems. I thought the best approach would be to handle some of the original feedback in the code before I came backto ping lkml. I discussed things a little offline with Andi Kleen. He suggested I focus on the simpler i/o regions first, then come back to handling main memory once I had that done and had gotten feedback on it. I've worked on a mechanism (cachemap) to track what type of caching a region of memory is currently mapped as. when a new region of memory is mapped, cachemap is queried to make sure the new region's caching type matches the old type (or is compatible with the old type). if the cachemap query succeeds, it's safe to map the new i/o region, otherwise it's not safe. for the first pass, I focused on testing ioremap. so the cachemap queries are only made from ioremap. I also added code to have the mtrr code call the cachemap code (in this case, it's a report rather than a query to indicate the mapping's already made). I've made a few test runs on systems here, and it seems to work fairly well. this current patch includes the original PAT support and the new cachemap mechanism. note that the cachemap mechanism does not actually change any caching attributes, it only keeps track of the attributes and tests regions. I think the end idea would be that drivers would use the normal ioremap/change_page_attr/remap_page_range mechanisms like they already do, and these mechanisms would in turn use cachemap to make sure there's no conflicts. I'm completely open to how any specific details should work, and any changes needed to be made. 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