Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S263557AbUDMPnY (ORCPT ); Tue, 13 Apr 2004 11:43:24 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S263564AbUDMPnY (ORCPT ); Tue, 13 Apr 2004 11:43:24 -0400 Received: from host213-123-250-229.in-addr.btopenworld.com ([213.123.250.229]:3372 "EHLO 2003SERVER.sbs2003.local") by vger.kernel.org with ESMTP id S263557AbUDMPnW (ORCPT ); Tue, 13 Apr 2004 11:43:22 -0400 thread-index: AcQhbmbqWiLsIY+NTam1dWc72X6d9A== X-Sieve: Server Sieve 2.2 In-Reply-To: <1081591559.25144.174.camel@gaston> References: <4077A542.8030108@nortelnetworks.com> <1081591559.25144.174.camel@gaston> MIME-Version: 1.0 Message-ID: <000001c4216e$66eace80$d100000a@sbs2003.local> Cc: "linuxppc-dev list" , "Chris Friesen" , "Linux Kernel list" From: "Segher Boessenkool" Subject: Re: want to clarify powerpc assembly conventions in head.S and entry.S Date: Tue, 13 Apr 2004 16:45:53 +0100 To: X-Mailer: Apple Mail (2.613) X-MIMETrack: Itemize by SMTP Server on D12ML044/12/M/IBM(Release 6.0.2CF2|July 23, 2003) at 13/04/2004 17:10:20,Serialize by Router on D12ML044/12/M/IBM(Release 6.0.2CF2|July 23, 2003) at 13/04/2004 17:10:24,Serialize complete at 13/04/2004 17:10:24 Content-Transfer-Encoding: 7bit Content-Type: text/plain; format=flowed; charset="US-ASCII" X-Mailing-List: X-Loop: linuxppc-dev@lists.linuxppc.org Envelope-to: paul@sumlocktest.fsnet.co.uk Content-Class: urn:content-classes:message X-me-spamlevel: not-spam Importance: normal X-me-spamrating: 6.400914 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.0 X-OriginalArrivalTime: 13 Apr 2004 15:45:53.0203 (UTC) FILETIME=[6709C830:01C4216E] Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1237 Lines: 40 >> stwcx. r0,0,r1 /* to clear the reservation */ >> >> I don't see the corresponding lwarx instruction. What reservation is >> it >> referring to? > > This is to clear any possible pending reservation if any. The problem > is > that the reservation mecanism only works accross multiple CPUs. A > normal > store at an address covered by a reservation on the same CPU will not > break > the reservation. Thus, to protect from that, any interrupt or exception > makes sure to return to the normal code flow with any pending > reservation > cleared. Worse, it is allowed for a PowerPC implementation to not check if stwcx. and stdcx. refer to the same address as the preceding lwarx or ldarx . So, a store conditional insn can succeed because the cpu holds some *other* reservation. Therefore, the kernel has to clear any reservation that might not have been generated by the user code it is returning to. Segher ** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/ - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/