Date: Tue, 13 Apr 2004 11:40:02 -0500
From: Terence Ripperda <tripperda@nvidia.com>
To: Manfred Spraul <manfred@colorfullife.com>
Cc: Terence Ripperda <tripperda@nvidia.com>, linux-kernel@vger.kernel.org
Subject: Re: PAT support
Message-ID: <20040413164002.GB453@hygelac>
Reply-To: Terence Ripperda <tripperda@nvidia.com>
References: <407B7BDE.5030002@colorfullife.com>
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oh, good catch. we added comments detailing this to an internal evaluation stand-alone pat module for pci express testing (the same pat.c/pat.h files as a standalone module), and I forgot to propogate those comments to this patch.

here's a snippet of our comments:

/* Here is the PAT's default layout on ia32 cpus at boot/reset.
 * This is table 10-12 in the IA-32 Intel Architecture Software Developer's
 * Manual Volume 3: System Programming Guide.
 * PAT0: Write Back
 * PAT1: Write Through
 * PAT2: Uncached (/ Uncacheable on Athlon cpus)
 * PAT3: Uncacheable
 * PAT4: Write Back
 * PAT5: Write Through
 * PAT6: Uncached (/ Uncacheable on Athlon cpus)
 * PAT7: Uncacheable
 * 
 * Rather than mucking with the PAT entries too much, we'll only replace one
 * entry with Write Combining. Ideally, we'd do that to one of the latter 4
 * entries, but due to errata in the P3/P4 cpus, we can only use the first
 * four entries reliably.
 *
 * For that reason, we'll replace PAT1: Write Through with Write Combine.
 * 
 * For more details about these errata, see Intel Pentium III Processor
 * Specification Update, errata E.27 (Upper Four PAT Entries Not Usable With
 * Mode B or Mode C Paging) and Intel Pentium IV Processor Specification
 * Update, errata N46 (PAT Index MSB May Be Calculated Incorrectly)
 */

rather than reprogramming all of the pats (compare the above table to the below table), we only replaced one entry with write-combining. I could just update cachemap with the corrected comments, or go ahead and only update the one pat entry, whichever everyone prefers.

Thanks,
Terence

On Mon, Apr 12, 2004 at 10:34:22PM -0700, manfred@colorfullife.com wrote:
> Hi Terence,
> 
> in your patch, you write
> +/* Here is the PAT's default layout on ia32 cpus when we are done.
> + * PAT0: Write Back
> + * PAT1: Write Combine
> + * PAT2: Uncached
> + * PAT3: Uncacheable
> + * PAT4: Write Through
> + * PAT5: Write Protect
> + * PAT6: Uncached
> + * PAT7: Uncacheable
> 
> Is that layout possible?
> There is an errata in the B2 and C1 stepping of the Pentium 4 cpus that 
> results in incorrect PAT numbers: the highest bit is ignored by the CPU 
> under some circumstances. There's a similar errata (E27) that affects 
> all Pentium 3 cpus: The highest bit is always ignored.
> I think we need a fallback to 4 PAT entries.
> 
> --
>     Manfred
> 
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