Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S264134AbUFFVNR (ORCPT ); Sun, 6 Jun 2004 17:13:17 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S264147AbUFFVNR (ORCPT ); Sun, 6 Jun 2004 17:13:17 -0400 Received: from gate.crashing.org ([63.228.1.57]:38018 "EHLO gate.crashing.org") by vger.kernel.org with ESMTP id S264134AbUFFVNK (ORCPT ); Sun, 6 Jun 2004 17:13:10 -0400 Subject: [PATCH] (urgent) ppc32: Fix CPUs with soft loaded TLB From: Benjamin Herrenschmidt To: Andrew Morton Cc: Linus Torvalds , Linux Kernel list Content-Type: text/plain Message-Id: <1086556255.1859.14.camel@gaston> Mime-Version: 1.0 X-Mailer: Ximian Evolution 1.4.6 Date: Sun, 06 Jun 2004 16:10:56 -0500 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2168 Lines: 61 Hi ! The recent introduction of ptep_set_access_flags() with the optimisation of not flushing the TLB unfortunately broke ppc32 CPUs with no hash table. The data access exception code path in assembly for these doesn't properly deal with the case where the TLB entry is present with the wrong PAGE_RW and will just call do_page_fault again instead of just replacing the TLB entry. Fixing the asm code for all the different CPU types affected (yah, embedded PPCs all have different MMUs =P) is painful and need testing I can't do at the moment, so here's a fix that will just flush the TLB page when changing the access flags on non-hash based machines. Please apply. Signed-off-by: Benjamin Herrenschmidt ===== include/asm-ppc/pgtable.h 1.33 vs edited ===== --- 1.33/include/asm-ppc/pgtable.h 2004-05-26 09:56:17 -05:00 +++ edited/include/asm-ppc/pgtable.h 2004-06-06 16:02:27 -05:00 @@ -555,8 +555,12 @@ (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); pte_update(ptep, 0, bits); } + #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - __ptep_set_access_flags(__ptep, __entry, __dirty) + do { \ + __ptep_set_access_flags(__ptep, __entry, __dirty); \ + flush_tlb_page_nohash(__vma, __address); \ + } while(0) /* * Macro to mark a page protection value as "uncacheable". ===== arch/ppc/mm/tlb.c 1.10 vs edited ===== --- 1.10/arch/ppc/mm/tlb.c 2004-02-04 23:00:14 -06:00 +++ edited/arch/ppc/mm/tlb.c 2004-06-06 16:01:05 -05:00 @@ -67,6 +67,17 @@ } /* + * Called by ptep_set_access_flags, must flush on CPUs for which the + * DSI handler can't just "fixup" the TLB on a write fault + */ +void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr) +{ + if (Hash != 0) + return; + _tlbie(addr); +} + +/* * Called at the end of a mmu_gather operation to make sure the * TLB flush is completely done. */ - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/