Date: Sat, 19 Jun 2004 01:34:48 +0100
From: Ian Molton <spyro@f2s.com>
To: linux-kernel@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, greg@kroah.com, tony@atomide.com,
       david-b@pacbell.net, jamey.hicks@hp.com, joshua@joshuawise.com,
       jgarzik@pobox.com
Subject: Re: DMA API issues
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On Fri, 18 Jun 2004 20:22:07 -0400
Jeff Garzik <jgarzik@pobox.com> wrote:

> > my CPU can write directly to this 32K of SRAM. the chip can DMA from
> > it.
> 
> 
> Yes, write via MMIO.  Non-local RAM is not DMA.

I fail to see your point. this is NOT MMIO. in MMIO you write and the
device reads as you write. in DMA, you write and then tell the chip to
read from the memory you wrote to.

this is exactly what Im talking about.

Heres what the DMA mapping code deals with:

CPU-----host bus------>RAM-----io bus---->device


and heres what I have:

CPU-----host bus----->RAM-----io bus----->device

the *only* difference is that the RAM in the first case is SDRAM and in
the latter is SRAM. the type of RAM is irrelevant to the DMA system.

I *could* (at great expense) replace the SDRAM in a PC with SRAM. DMA
would still work the same way.

sure, the SRAM is *on* the die of my OCHI/multi-io controller. whats
that got to do with it?

and theres the other issue - if I made an ohci allocator for the SRAM
I'd have to partition off a small ammount ONLY for OHCI. with only 32K
to begin with thats a huge penalty for all the other devices in the
multi IO chip. a bus level DMA allocator solves this AND makes drivers
cleaner/more maintainable.

What more do you want?
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