From: Joshua Wise <joshua@joshuawise.com>
Organization: JoshuaWise.com DevStudios
To: Ian Molton <spyro@f2s.com>
Subject: Re: DMA API issues... summary
Date: Sun, 20 Jun 2004 16:49:33 -0400
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Jumping into the discussion from the middle of nowhere ......

> Single chip devices may be able to either access system memory directly, or
> may only be able to access their internal SRAM pool. in the case of the
> latter the system can either directly access the SRAM or not, depending on
> the device/bus setup. Its possible the devices may have more than one
> non-continuous SRAM mapping.
>
> The same goes for SOC devices, however they could come in two 'classes'. In
> one type, we would essentially have multiple independant devices in a
> single chip. In another case (which appears to be fairly common) we can
> have multiple devices sharing a common SRAM pool. its also possible to have
> some devices sharing the pool and some having their own in the same chip.

First off ... Why just say the internal SRAM pool? I think it woudl be better 
to say that the devices can only access their own address space, and can only 
DMA from a subset of that (which may be the full original set, QED)

Second... Remember that the SOC can also be the CPU! At least on XScale, there 
are some portions that we can DMA from main memory (I think USB is one).

Of course this might not be at all relevant to the discussion, and of course I 
could be using my rectally-based knowledge, but I _THINK_ that this is 
correct.

joshua
- -- 
Joshua Wise | www.joshuawise.com
GPG Key     | 0xEA80E0B3
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