Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S266467AbUFUVHL (ORCPT ); Mon, 21 Jun 2004 17:07:11 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S266468AbUFUVHL (ORCPT ); Mon, 21 Jun 2004 17:07:11 -0400 Received: from dragnfire.mtl.istop.com ([66.11.160.179]:31978 "EHLO dsl.commfireservices.com") by vger.kernel.org with ESMTP id S266467AbUFUVHJ (ORCPT ); Mon, 21 Jun 2004 17:07:09 -0400 Date: Mon, 21 Jun 2004 17:09:17 -0400 (EDT) From: Zwane Mwaikambo To: James Cleverdon Cc: Kirill Korotaev , linux-kernel@vger.kernel.org Subject: Re: can TSC tick with different speeds on SMP? In-Reply-To: <200406211350.09295.jamesclv@us.ibm.com> Message-ID: References: <200406211350.09295.jamesclv@us.ibm.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 761 Lines: 18 On Mon, 21 Jun 2004, James Cleverdon wrote: > IIRC, in the IA64 manuals Intel, by carefully not making any guarantees > to the contrary, reserved the right to have the TSC-equivalent register > not be synchronized either to the bus clock or the CPU clock. > > This doesn't directly apply to IA32, but may give a hint as to their > future intentions. The intel MP1.4 specification also allows for processors of varying capabilities, this would include different clock speeds resulting in differing TSC frequencies. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/