Date: Tue, 7 Sep 2004 17:08:07 -0700
From: "David S. Miller" <davem@davemloft.net>
To: Zachary Amsden <zach@vmware.com>
Cc: linux-kernel@vger.kernel.org, davej@codemonkey.org.uk, hpa@zytor.com,
       bgerst@didntduck.org, Riley@Williams.Name
Subject: Re: PROBLEM: x86 alignment check bug
Message-Id: <20040907170807.2e8bba1d.davem@davemloft.net>
In-Reply-To: <413E498D.4020807@vmware.com>
References: <413E498D.4020807@vmware.com>
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On Tue, 07 Sep 2004 16:51:41 -0700
Zachary Amsden <zach@vmware.com> wrote:

> Clearly, this is not correct.  Considering how difficult the fix is (the 
> kernel must disassemble the faulting instruction and use register 
> information to determine the faulting address),

While it is more difficult to disassemble x86 opcodes,
what you describe is exactly how we handle this on
sparc64.  In fact we do opcode decoding for most fault
types.
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