Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S262586AbUKLRx2 (ORCPT ); Fri, 12 Nov 2004 12:53:28 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S262588AbUKLRx2 (ORCPT ); Fri, 12 Nov 2004 12:53:28 -0500 Received: from mms3.broadcom.com ([63.70.210.38]:4359 "EHLO mms3.broadcom.com") by vger.kernel.org with ESMTP id S262586AbUKLRwe convert rfc822-to-8bit (ORCPT ); Fri, 12 Nov 2004 12:52:34 -0500 X-Server-Uuid: 062D48FB-9769-4139-967C-478C67B5F9C9 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: [PATCH] pci-mmconfig fix for 2.6.9 Date: Fri, 12 Nov 2004 09:52:17 -0800 Message-ID: Thread-Topic: [PATCH] pci-mmconfig fix for 2.6.9 Thread-Index: AcTHxD1dIvWKB170S7i0ZznDIcHSdAAR51xAADSs9bA= From: "Michael Chan" To: "Andi Kleen" cc: linux-kernel@vger.kernel.org, linux-pci@atrey.karlin.mff.cuni.cz, akpm@osdl.org, greg@kroah.com, "Durairaj, Sundarapandian" X-WSS-ID: 6D8A27D81TG2663811-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1905 Lines: 53 On Wednesday, November 10, 2004 11:58 PM Andi Kleen wrote: > Where is it guaranteed that these writes are non posted? Intel chipset engineer confirmed that they are non-posted. Here are excerpts from some email exchange with Intel. We reported the out-of-spec dummy read problem to Intel a while back. Begin forwarded message: Hi Michael, I have checked our chipset engineer. He specified that the mmconfig is truly non posted and memory cycles will be completed only after the config write are finished. So I think flushing is not necessary and readl can be removed. Thanks, Sundar -----Original Message----- From: Michael Chan [mailto:mchan@broadcom.com] Sent: Friday, November 05, 2004 5:08 AM To: Durairaj, Sundarapandian Subject: RE: MMCONFIG Bug Hi Sundar, Thanks for the update. I agree that config cycles are non-posted and therefore flushing is unnecessary. However, since config cycles are not directly generated by the CPU, it is a bit more complicated. When the CPU issues the memory cycle (writel) to the chipset, the chipset will translate the memory cycle into a PCI Express config request on the appropriate PCI Express link. The target device will then return a completion. Is the memory cycle to the chipset posted or not? In other words, does the chipset complete the memory cycle before issuing the config cycle, or does it issue the config cycle and wait for completion before completing the memory cycle (writel) from the CPU? If the latter is true, then it is unnecessary to flush the writel as it is truly non-posted. If the former is true, I think flushing is still necessary. Just wanted to confirm this. Thanks, Michael - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/