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From:   "S.j. Wang" <shengjiu.wang@nxp.com>
To:     Nicolin Chen <nicoleotsuka@gmail.com>,
        Daniel Baluta <daniel.baluta@nxp.com>
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Subject: Re: [PATCH] ARM: dts: imx: Add mclk0 clock for SAI
Thread-Topic: [PATCH] ARM: dts: imx: Add mclk0 clock for SAI
Thread-Index: AdT4uuVRukjA0rRgTeifBXCEXrMHAQ==
Date:   Mon, 22 Apr 2019 03:30:26 +0000
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Hi

>=20
>=20
> On Sat, Apr 20, 2019 at 09:12:52AM +0000, Daniel Baluta wrote:
> > From: Shengjiu Wang <shengjiu.wang@nxp.com>
> >
> > SAI has 4 clock sources, which can be selected using MSEL bit of SAI
> > TCR2 register.
>=20
> I have a doubt at this statement. As far as I can understand, this MSEL i=
s
> probably used by its internal clock MUX, so it's not really proving that =
SAI
> has 4 MCLK inputs. What I know is that SAI block itself only has 3 MCLK
> inputs as we defined in DT. It's just internally connects bus clock or MC=
LK1
> to input0 of clock MUX's and connects MCLK[1-3] to input[1-3]. So adding =
an
> MCLK0 here doesn't sound a right way to me. Unless someone can justify
> for it, I think we should just fix it from driver side.
>=20
> Thanks
> Nicolin
>

The MSEL bit width is 2 bit, so there is 4 options,  the MCLK0 maybe the sa=
me input as
MCLK1 or bus clock as you said, so we think may be better to show this rela=
tion in DT,=20
And this is DT's capability.  Driver don't care about which clock connect t=
o MCLK0,=20
it only need to know there is 4 MCLK from DT.=20

Best regards
Wang shengjiu

=20