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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: k8+iWtl4YKtjRDfyauvteMccHRRqiSbDxGt9e9sjxqi0p55GhSrByXzj3/+R4EIB4knFcifX6sS3a7I9sRdvZ2XQjODRvMmV1AzmlDsHeDn8d6xvsRNTb3AlLlCCq49QpDfZ0N5cJCGHtBY1kfw5pNEOG4yNaDreHhAcNvPEWncIP5oDhVPQeKnSXERhfCet8sL9fSTXoChQPeL1srcJzU2s62o3jQt32K3Jk50V+CS/qHKX7W5o/c7cvenKVKCxyY7Xrqs2N08xujrRvFfhFiu5wlA2PGqsVgNtfedwNQzRgvGddPPi1MYrL1n0QTjQ4ExP7DA2qpPwzy1PjZbWv7RmpF+YrKsOpG4XxsxLDYavgF8T27784pgBFQQinbece/HxDSxSCe6NEiISBPTzK4R+RhaD50UWZdtaL3sCiyk= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0bacf32-512a-43c9-1f8d-08d6c6ee347b X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2019 06:46:10.2462 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3755 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Shawn Best Regards! Anson Huang > -----Original Message----- > From: Anson Huang > Sent: Monday, April 22, 2019 8:52 AM > To: Shawn Guo > Cc: stefan.wahren@i2se.com; enric.balletbo@collabora.com; linux- > kernel@vger.kernel.org; heiko@sntech.de; marc.w.gonzalez@free.fr; > ezequiel@collabora.com; catalin.marinas@arm.com; > s.hauer@pengutronix.de; will.deacon@arm.com; Abel Vesa > ; bjorn.andersson@linaro.org; Andy Gross > ; jagan@amarulasolutions.com; > kernel@pengutronix.de; dl-linux-imx ; olof@lixom.net; > horms+renesas@verge.net.au; festevam@gmail.com; robh@kernel.org; > linux-arm-kernel@lists.infradead.org; l.stach@pengutronix.de > Subject: RE: [PATCH 1/2] soc: imx-sc: add i.MX system controller soc driv= er > support >=20 > Hi, Shawn >=20 > Best Regards! > Anson Huang >=20 > > -----Original Message----- > > From: Shawn Guo [mailto:shawnguo@kernel.org] > > Sent: Sunday, April 21, 2019 3:42 PM > > To: Anson Huang > > Cc: stefan.wahren@i2se.com; enric.balletbo@collabora.com; linux- > > kernel@vger.kernel.org; heiko@sntech.de; marc.w.gonzalez@free.fr; > > ezequiel@collabora.com; catalin.marinas@arm.com; > > s.hauer@pengutronix.de; will.deacon@arm.com; Abel Vesa > > ; bjorn.andersson@linaro.org; Andy Gross > > ; jagan@amarulasolutions.com; > > kernel@pengutronix.de; dl-linux-imx ; > > olof@lixom.net; > > horms+renesas@verge.net.au; festevam@gmail.com; robh@kernel.org; > > linux-arm-kernel@lists.infradead.org; l.stach@pengutronix.de > > Subject: Re: [PATCH 1/2] soc: imx-sc: add i.MX system controller soc > > driver support > > > > On Sun, Apr 21, 2019 at 03:40:00PM +0800, Shawn Guo wrote: > > > On Thu, Apr 11, 2019 at 06:49:12AM +0000, Anson Huang wrote: > > > > i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller > > > > inside, the system controller is in charge of controlling power, > > > > clock and fuse etc.. > > > > > > > > This patch adds i.MX system controller soc driver support, Linux > > > > kernel has to communicate with system controller via MU (message > > > > unit) IPC to get soc revision, uid etc.. > > > > > > > > With this patch, soc info can be read from sysfs: > > > > > > > > i.mx8qxp-mek# cat /sys/devices/soc0/family Freescale i.MX > > > > > > > > i.mx8qxp-mek# cat /sys/devices/soc0/soc_id i.MX8QXP > > > > > > > > i.mx8qxp-mek# cat /sys/devices/soc0/machine Freescale i.MX8QXP > MEK > > > > > > > > i.mx8qxp-mek# cat /sys/devices/soc0/revision > > > > 1.1 > > > > > > > > i.mx8qxp-mek# cat /sys/devices/soc0/soc_uid > > > > 7B64280B57AC1898 > > > > > > > > Signed-off-by: Anson Huang > > > > --- > > > > drivers/soc/imx/Kconfig | 7 ++ > > > > drivers/soc/imx/Makefile | 1 + > > > > drivers/soc/imx/soc-imx-sc.c | 220 > > > > +++++++++++++++++++++++++++++++++++++++++++ > > > > 3 files changed, 228 insertions(+) create mode 100644 > > > > drivers/soc/imx/soc-imx-sc.c > > > > > > Rather than creating a new driver, please take a look at Abel's > > > generic > > > i.MX8 SoC driver, and see if it can be extended to cover i.MX8QXP. > > > > Forgot to give pointer to Abel's driver. > > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgit= . > > ker > nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fshawnguo%2Flinux.git% > > > 2Fcommit%2F%3Fh%3Dimx%2Fdrivers%26id%3Da7e26f356ca12906a164d83c > > > 9e9f8527ee7da022&data=3D02%7C01%7Canson.huang%40nxp.com%7C9 > > > e2705d7449b4c2e23ed08d6c62ce0bb%7C686ea1d3bc2b4c6fa92cd99c5c3016 > > > 35%7C0%7C0%7C636914293400307709&sdata=3D6ySEs%2B4SE8bvcBCkfoi > > VBafseAYthTED9%2F5qcf25xds%3D&reserved=3D0 > > >=20 > Got it, I didn't notice that this patch bas been accepted, I will redo th= e patch > based on it, thanks. I have sent the new patch set to support i.MX8QXP SoC revision based on gen= eric i.MX8 SoC driver, however, the Kconfig modification is NOT good, it may break i.M= X8MQ if IMX_SCU is NOT enabled, although we can add some warp function for SCU firmware API= call to fix it, but after further thought and discussion with Dong Aisheng, I think we may = need to roll back to use this patch series to create a new SoC driver dedicated for i.MX8 SoCs with system controller inside, such as i.MX8QXP, i.MX8QM etc., the reason a= re as below: For i.MX8MQ/i.MX8MM: 1. SoC driver does NOT depends on i.MX SCU firmware, so no need to use pla= tform driver probe model, just device_init phase call is good enough; 2. The SoC driver no need to depends on IMX_SCU, so it can be always built= in, no need to check IMX_SCU config; 3. The fuse check for CPU speed grading, HDCP status, NoC settings etc. co= uld be added to this driver, but they are ONLY for i.MX8MQ/i.MX8MM etc.. For i.MX8QXP/i.MX8QM: 1. SoC driver MUST depends on IMX_SCU; 2. MUST use platform model to support defer probe; 3. No fuse check for CPU speed grading. So, I guess the reused code for i.MX8MQ and i.MX8QXP is ONLY those part of = creating SoC id device node (less than 30% I think), all other functions are implemented in total different ways, = that is why I created the imx_sc_soc driver in this patch series, so do you think we can add new SoC driver for i.MX8 S= oC with SCU inside? Putting 2 different architecture SoCs' driver into 1 file looks like NOT making enough sense. Anson. >=20 > Anson. >=20 > > Shawn